Power-up sequencing and high voltage protection for charge pump converters
Certain aspects of the present disclosure generally relate to methods and apparatus for powering up a charge pump converter and providing protection and soft-start circuitry therefor. One example charge pump converter generally includes a first transistor and a second transistor coupled in series between an input voltage node and an output voltage node of the charge pump converter, a first capacitive element having a first terminal coupled to a node between the first and second transistors, and a first switch coupled to the input voltage node, the first switch being configured to selectively enable a first drive circuit having an output coupled to a control terminal of the second transistor.
1. A charge pump converter comprising:
a first transistor and a second transistor coupled in series between an input voltage node and an output voltage node;
a first capacitive element having a first terminal coupled to a node between the first and second transistors;
a first switch coupled to the input voltage node, the first switch being configured to selectively enable a first drive circuit having an output coupled to a control terminal of the second transistor; and
a first diode device having a cathode coupled to the input voltage node and an anode coupled to a first power supply node of the first drive circuit, a second power supply node of the first drive circuit being coupled to the output voltage node, wherein the first switch is coupled in parallel with the first diode device.
2. The charge pump converter of claim 1 , wherein the first switch is configured to selectively enable the first drive circuit based on a voltage at the output voltage node exceeding a reference voltage.
3. The charge pump converter of claim 1 , further comprising:
a voltage divider coupled to the input voltage node;
a comparator having a first input coupled to a tap of the voltage divider and a second input coupled to the output voltage node; and
a selectively enabled current source coupled between the input voltage node and the output voltage node.
4. The charge pump converter of claim 3 , wherein the voltage divider comprises:
a first resistive element coupled between the input voltage node and the tap of the voltage divider; and
a second resistive element coupled between the tap of the voltage divider and a reference potential node for the charge pump converter, the first and second resistive elements having a same resistance.
5. The charge pump converter of claim 1 , further comprising a second capacitive element coupled between the output voltage node and a reference potential node for the charge pump converter.
6. The charge pump converter of claim 1 , further comprising:
a second drive circuit having an output coupled to a control terminal of the first transistor;
a second diode device having a cathode coupled to a first power supply node of the second drive circuit and an anode coupled to at least one of the first power supply node of the first drive circuit or the anode of the first diode device; and
a second switch coupled in parallel with the second diode device.
7. The charge pump converter of claim 6 , further comprising a second capacitive element having a first terminal coupled to the node between the first and second transistors and a second terminal coupled to at least one of the cathode of the second diode device or the first power supply node of the second drive circuit.
8. The charge pump converter of claim 1 , further comprising:
a third transistor and a fourth transistor coupled in series between the output voltage node and a reference potential node for the charge pump converter; and
a second drive circuit having an output coupled to a control terminal of the third transistor.
9. The charge pump converter of claim 8 , wherein a second terminal of the first capacitive element is coupled to a node between the third and fourth transistors.
10. The charge pump converter of claim 8 , further comprising:
a diode device having a cathode coupled to the node between the first and second transistors and an anode coupled to a first power supply node of the second drive circuit, a second power supply node of the second drive circuit being coupled to a node between the third and fourth transistors; and
a second switch coupled in parallel with the diode device.
11. The charge pump converter of claim 8 , further comprising a selectively enabled current source coupled between:
a node between the third and fourth transistors; and
the reference potential node for the charge pump converter.
12. The charge pump converter of claim 11 , further comprising a comparator having a first input coupled to a voltage reference node and a second input coupled to the node between the third and fourth transistors.
13. The charge pump converter of claim 8 , wherein a gate of the third transistor is coupled to the output of the second drive circuit, wherein a drain of the third transistor is coupled to the output voltage node, and wherein a source of the third transistor is coupled to a drain of the fourth transistor.
14. The charge pump converter of claim 1 , wherein a gate of the second transistor is coupled to the output of the first drive circuit, wherein a source of the second transistor is coupled to the output voltage node, and wherein a drain of the second transistor is coupled to a source of the first transistor.
15. The charge pump converter of claim 1 , wherein the first drive circuit comprises a complementary metal-oxide semiconductor (CMOS) drive circuit.
16. A method of powering up a charge pump converter, the method comprising:
enabling a current source coupled between an input voltage node and an output voltage node of the charge pump converter;
after enabling the current source, comparing a voltage associated with the output voltage node with a reference voltage; and
after the voltage associated with the output voltage node meets or exceeds the reference voltage based on the comparison, outputting an indication for the charge pump converter;
closing a first switch to enable a first drive circuit based on the indication, a first transistor and a second transistor being coupled in series between the input voltage node and the output voltage node of the charge pump converter, and the first drive circuit having an output coupled to a control terminal of the second transistor.
17. The method of claim 16 , further comprising determining a voltage at the output voltage node has exceeded a reference voltage, wherein closing the first switch is based on the determination.
18. The method of claim 16 , wherein enabling the current source charges a capacitive element coupled between the output voltage node and a reference potential node for the charge pump converter.
19. The method of claim 16 , wherein enabling the current source comprises closing a second switch coupled in series with the current source between the input voltage node and the output voltage node.
20. The method of claim 16 , further comprising generating the reference voltage with a voltage divider comprising:
a first resistive element coupled between the input voltage node and a tap of the voltage divider; and
a second resistive element coupled between the tap of the voltage divider and a reference potential node for the charge pump converter, the first and second resistive elements having a same resistance.
21. The method of claim 16 , further comprising outputting a gate drive signal from the first drive circuit to turn on the second transistor, wherein a source of the second transistor is coupled to the output voltage node and wherein a drain of the second transistor is coupled to a capacitive element.
22. The method of claim 16 , wherein:
the first switch is coupled in parallel with a first diode device;
the first diode device has a cathode coupled to the input voltage node and an anode coupled to a first power supply node of the first drive circuit; and
a second power supply node of the first drive circuit is coupled to the output voltage node.
23. The method of claim 22 , further comprising closing a second switch coupled in parallel with a second diode device, wherein:
a second drive circuit has an output coupled to a control terminal of the first transistor;
the second diode device has a cathode coupled to a first power supply node of the second drive circuit and an anode coupled to at least one of the first power supply node of the first drive circuit or the anode of the first diode device; and
a first capacitive element has a first terminal coupled to a node between the first and second transistors and a second terminal coupled to at least one of the cathode of the second diode device or the first power supply node of the second drive circuit.
24. The method of claim 23 , further comprising enabling a current source coupled between a first terminal of a second capacitive element and a reference potential node for the charge pump converter, wherein:
a second terminal of the second capacitive element is coupled to the node between the first and second transistors;
a third transistor and a fourth transistor are coupled in series between the output voltage node and the reference potential node for the charge pump converter;
the first terminal of the second capacitive element is coupled to a node between the third and fourth transistors; and
a third drive circuit has an output coupled to a control terminal of the third transistor.
25. The method of claim 24 , further comprising:
after enabling the current source, comparing a voltage associated with the first terminal of the second capacitive element with a reference voltage; and
after the voltage associated with the first terminal of the second capacitive element meets or exceeds the reference voltage based on the comparison, turning on the fourth transistor for a clock cycle of the charge pump converter.
26. The method of claim 25 , further comprising closing a third switch coupled in parallel with a third diode device, wherein:
the third diode device has a cathode coupled to the node between the first and second transistors and an anode coupled to a first power supply node of the third drive circuit; and
a second power supply node of the third drive circuit is coupled to the node between the third and fourth transistors.