Bio and chemical sensor with increased sensitivity
View Patent ↗An ISFET structure and method for creating the same is provided. A device with a substrate is provided, an insulator layer is deposited over the substrate, and a material layer is deposited over the insulator layer, where the material layer can be a membrane, including a porous membrane, which can reduce the parasitic capacitance of a bio-species or chemical that can be applied with the device.
1. A method for forming an ion-sensitive field-effect transistor comprising:
providing a substrate;
depositing an insulator layer on the substrate;
depositing a sacrificial layer on the insulator layer; and
depositing, over the insulator layer, at least one material layer for reducing a parasitic capacitance associated with a bio-species or chemical solution that can be deposited over the insulator layer, wherein depositing the at least one material layer comprises:
depositing a nitride layer over the insulator layer, wherein depositing the nitride layer over the insulator layer comprises depositing the nitride layer over the sacrificial layer; and
etching the nitride layer to form a plurality of nitride pillars forming a porous membrane layer over the insulator layer.
2. The method of claim 1 , wherein etching the nitride layer to form the plurality of nitride pillars forming the porous membrane layer further comprises forming an opening of a plurality of openings between adjacent nitride pillars of the plurality of nitride pillars over the insulating layer.
3. The method of claim 1 , further comprising: depositing a second sacrificial material layer over the porous membrane layer.
4. The method of claim 3 , further comprising:
forming a plurality of spacers over the substrate and in contact with the second sacrificial material layer; and
forming an interconnect structure over the second sacrificial material layer.
5. The method of claim 4 , wherein the interconnect structure comprises:
i) a plurality of metal contacts in contact with at least one layer of the device and
ii) an inter-connecting dielectric layer in contact with the plurality of metal contacts and the substrate.
6. The method of claim 5 , further comprising:
creating a plurality of trenches through the interconnecting dielectric layer; and
removing both the sacrificial material layer and the second sacrificial material layer by applying an etchant through the plurality of trenches, wherein the porous membrane layer is a silicon-nitride layer, and wherein the sacrificial layer and the second sacrificial material layer are both silicon-germanium layers.
7. A method for forming an ion-sensitive field-effect transistor comprising:
providing a substrate;
depositing an insulator layer on the substrate;
depositing a sacrificial layer on the insulator layer;
depositing, after the sacrificial layer and over the insulator layer, at least one material layer for reducing a parasitic capacitance associated with a bio-species or chemical solution that can be deposited over the insulator layer, wherein depositing the at least one material layer comprises:
depositing a nitride layer over the insulator layer;
etching the nitride layer to form a plurality of nitride pillars forming a porous membrane layer over the insulator layer; and
depositing a second sacrificial material layer over the porous membrane layer.
8. The method of claim 7 , wherein depositing the nitride layer over the insulator layer comprises depositing the nitride layer over the sacrificial layer.
9. The method of claim 7 , wherein etching the nitride layer to form the plurality of nitride pillars forming the porous membrane layer further comprises forming an opening of a plurality of openings between adjacent nitride pillars of the plurality of nitride pillars over the insulating layer.
10. The method of claim 7 , further comprising:
forming a plurality of spacers over the substrate and in contact with the second sacrificial material layer; and
forming an interconnect structure over the second sacrificial material layer.
11. The method of claim 10 , wherein the interconnect structure comprises:
i) a plurality of metal contacts in contact with at least one layer of the device; and
ii) an inter-connecting dielectric layer in contact with the plurality of metal contacts and the substrate.
12. The method of claim 11 , further comprising:
creating a plurality of trenches through the interconnecting dielectric layer; and
removing both the sacrificial material layer and the second sacrificial material layer by applying an etchant through the plurality of trenches, wherein the porous membrane layer is a silicon-nitride layer, and wherein the sacrificial layer and the second sacrificial material layer are both silicon-germanium layers.