Method of making a high speed semiconductor device

1. A method of fabricating a semiconductor device, the method comprising:

forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip;

forming a first source/drain feature between the gate structure and the first edge structure;

forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is from about 1.5 to about 4.5 times greater than a distance between the gate structure and the second source/drain feature; and

implanting a buried channel in the semiconductor strip, wherein a top surface of the buried channel is spaced from a top surface of the semiconductor strip, a bottom surface of the buried channel is closer to the top surface of the semiconductor strip than a bottom surface of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.

2. The method of claim 1 , wherein the implanting the buried channel comprises implanting the buried channel having the dopant concentration under the gate structure ranging from about 1.7E18 cm −3 to about 2.0E20 cm −3 .

3. The method of claim 1 , wherein implanting the buried channel comprises implanting the buried channel at a depth from about 2 nanometers (nm) to about 7 nm below the top surface of the semiconductor strip.

4. The method of claim 1 , further comprising depositing an insulating material to form a first isolation region and a second isolation region, wherein the semiconductor strip is between the first isolation region and the second isolation region.

5. The method of claim 4 , further comprising forming the first edge structure partially overlaps the first isolation region.

6. The method of claim 5 , further comprising forming the second edge structure partially overlaps the second isolation region.

7. The method of claim 5 , wherein forming the first edge structure comprises forming the first edge structure having a length in a first direction parallel to the top surface of the semiconductor strip greater than a length of the gate structure in the first direction.

8. A method of fabricating a semiconductor device, the method comprising:

forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip, wherein a distance between the gate structure and the first edge structure is different from a distance between the gate structure and the second edge structure;

forming a first source/drain feature between the gate structure and the first edge structure;

forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature; and

implanting a buried channel in the semiconductor strip, wherein a top surface of the buried channel is spaced from a top surface of the semiconductor strip, a bottom surface of the buried channel is closer to the top surface of the semiconductor strip than a bottom surface of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.

9. The method of claim 8 , wherein forming the first source/drain feature comprises forming the first source/drain feature a same distance from the gate structure as from the first edge structure.

10. The method of claim 8 , wherein forming the second source/drain feature comprises forming the second source/drain feature closer to the second edge feature than the gate structure.

11. The method of claim 8 , wherein forming the first edge structure comprises forming the first edge structure entirely over the semiconductor strip.

12. The method of claim 8 , further comprising depositing an insulating material to define a first isolation region adjacent the semiconductor strip.

13. The method of claim 12 , wherein forming the first edge structure comprises forming the first edge structure partially over the first isolation region.

14. The method of claim 12 , wherein forming the first edge structure comprises forming the first edge structure entirely over the first isolation region.

15. A method of fabricating a semiconductor device, the method comprising:

forming a dummy gate structure, a dummy first edge structure and a dummy second edge structure on a semiconductor strip;

forming a first source/drain feature between the dummy gate structure and the dummy first edge structure;

forming a second source/drain feature between the dummy gate structure and the dummy second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature;

implanting a buried channel in the semiconductor strip, wherein a top surface of the buried channel is spaced from a top surface of the semiconductor strip, a bottom surface of the buried channel is closer to the top surface of the semiconductor strip than a bottom surface of the first source/drain feature, and a dopant concentration of the buried channel is highest under the dummy gate structure; and

replacing the dummy gate structure with an active gate structure.

16. The method of claim 15 , further comprising replacing the dummy first edge structure with a first edge structure having a different material from the dummy first edge structure.

17. The method of claim 16 , further comprising replacing the dummy first edge structure with a first edge structure having a different material from the dummy first edge structure.

18. The method of claim 15 , further comprising forming a gate contact over the active gate structure.

19. The method of claim 15 , further comprising forming a contact structure over the dummy first edge structure.

20. The method of claim 15 , wherein forming the dummy first edge structure comprises forming the dummy first edge structure at least partially over an isolation region.