Dynamic random access memory
A dynamic random access memory (DRAM) is provided and includes a base substrate. The base substrate includes a semiconductor substrate, a plurality of fins formed on the semiconductor substrate, and an isolation structure formed on the semiconductor substrate and covering portions of side surfaces of the plurality of fins. The dynamic random access memory further includes an interlayer dielectric layer formed over the base substrate and covering top surfaces of the plurality of fins and the isolation structure; and a memory structure, formed in an opening passing through the interlayer dielectric layer and each of the plurality of fins, the opening extending to and exposing a top surface of a portion of the isolation structure. The memory structure includes a first conductive layer, a memory medium layer on the first conductive layer, and a second conductive layer on the memory medium layer.
1. A dynamic random access memory, comprising:
a base substrate, including a semiconductor substrate, a plurality of fins formed on the semiconductor substrate, and an isolation structure formed on the semiconductor substrate and covering portions of side surfaces of the plurality of fins;
an interlayer dielectric layer formed over the base substrate and covering top surfaces of the plurality of fins and the isolation structure; and
a memory structure, formed in an opening passing through the interlayer dielectric layer and each of the plurality of fins, the opening extending to and exposing a top surface of a portion of the isolation structure,
wherein the memory structure includes a first conductive layer, a memory medium layer on the first conductive layer, and a second conductive layer on the memory medium layer.
2. The memory according to claim 1 , wherein:
a top surface of the first conductive layer on a side surface of the opening is below a top surface of the interlayer dielectric layer and the memory medium layer covers a portion of the side surface of the opening.
3. The memory according to claim 1 , wherein:
a top surface of the first conductive layer on a side surface of the opening leveling with a top surface of the interlayer dielectric layer.
4. The memory according to claim 1 , wherein:
the opening has first side surfaces opposing each other and second side surfaces opposing each other;
the first side surfaces are in contact with the second side surfaces, respectively;
the first conductive layer is formed on the first side surface;
the memory medium layer is formed on the first side surfaces, the second side surfaces and the bottom surface of the opening; and
the first side surfaces expose the plurality of fins.
5. The memory according to claim 4 , wherein:
the second side surface includes a first sub-side surface and a second sub-side surface;
the first sub-side surface exposes a side surface of the isolation structure; and
the second sub-side surface exposes a portion of the side surface of the interlayer dielectric layer.
6. The memory according to claim 1 , wherein:
the memory structure is one of a resistance-change memory structure having the memory medium layer made of a resistance-change material, a phase-change memory structure having the memory medium layer made of a phase-change material, and a capacitive memory structure having the memory medium layer made of a capacitive medium material.
7. The memory according to claim 1 , further comprising:
a select transistor electrically connected with the memory structure.
8. The memory according to claim 1 , wherein:
the first conductive layer is formed directly on the semiconductor substrate.
9. The memory according to claim 8 , wherein:
the first conductive layer exposes a portion of a bottom surface of the opening and the memory medium layer is formed directly on the portion of the bottom surface of the opening.
10. The memory according to claim 1 , wherein:
a top surface of the first conductive layer is below a bottom surface of the interlayer dielectric layer.