Semiconductor device and manufacturing method thereof
In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.
1. A method of manufacturing a negative capacitance structure, the method comprising:
forming an amorphous dielectric layer over a substrate;
forming a first metallic layer over the amorphous dielectric layer;
after the first metallic layer is formed, converting the amorphous dielectric layer to a ferroelectric dielectric layer including an orthorhombic crystal phase by performing an annealing operation followed by a cooling operation;
forming a second metallic layer;
forming a work function adjustment layer on the second metallic layer; and
forming a glue layer on the work function adjustment layer; and
forming a gate metal layer on the glue layer,
wherein the ferroelectric dielectric layer includes HfO 2 doped with Si in an amount of 2-6 mol %.
2. The method of claim 1 , wherein the annealing operation is performed at a temperature in a range from 700° C. to 1000° C. in an inert gas ambient.
3. The method of claim 1 , wherein the second metallic layer is formed after the cooling operation.
4. The method of claim 1 , wherein the first metallic layer includes TiN.
5. The method of claim 1 , wherein the second metallic layer is TaN.
6. The method of claim 1 , wherein the orthorhombic crystal phase is polycrystalline.
7. The method of claim 1 , wherein the ferroelectric dielectric layer includes the orthorhombic crystal phase in an amount of at least 80% and at least one of amorphous, monolithic and tetragonal phases.
8. A method of manufacturing a negative capacitance field effect transistor (NC-FET), the method comprising:
forming an amorphous dielectric layer over a semiconductor substrate; forming a capping metallic layer over the amorphous dielectric layer; after the capping metallic layer is formed, converting the amorphous dielectric layer to a ferroelectric dielectric layer including an orthorhombic crystal phase by performing an annealing operation followed by a cooling operation;
forming a barrier layer over the capping layer; forming a work function adjustment layer over the barrier layer; forming a glue layer on the work function adjustment layer; and forming a gate metal layer on the glue layer, wherein the annealing operation is performed at a temperature in a range from 700° C. to 1000° C. in an inert gas ambient for 10 seconds to 1 minute, wherein the ferroelectric dielectric layer includes Hf02 doped with Si in an amount of 2-6 mol %.
9. The method of claim 8 , wherein the ferroelectric dielectric layer includes HfO 2 containing Si or HfO 2 containing Zr.
10. The method of claim 8 , wherein the capping metallic layer includes TiN or TiN doped with Si.
11. The method of claim 10 , wherein the barrier layer is formed after the cooling operation.
12. The method of claim 11 , wherein the barrier layer is TaN.
13. The method of claim 8 , wherein the gate metal layer includes W.
14. The method of claim 13 , wherein the glue layer is made of Ti.
15. The method of claim 8 , further comprising forming an interfacial oxide layer over the semiconductor substrate before the amorphous dielectric layer is formed.
16. A method of manufacturing a negative capacitance field effect transistor (NC-FET), the method comprising:
forming an amorphous dielectric layer over a semiconductor substrate; forming a capping metallic layer over the amorphous dielectric layer; after the capping metallic layer is formed, converting the amorphous dielectric layer to a ferroelectric dielectric layer including an orthorhombic crystal phase by performing an annealing operation followed by a cooling operation; forming a barrier layer over the capping metallic layer; and forming a work function adjustment layer over the barrier layer, wherein the ferroelectric dielectric layer includes orthorhombic HfZr02 containing A1 or Ti, wherein the ferroelectric dielectric layer includes orthorhombic HfZrO 2 containing Al in an amount of 5-7 mol % or Ti in an amount of 2-5 mol %.
17. The method of claim 1 , wherein the first metallic layer includes TiN doped with Si.
18. The method of claim 8 , wherein the cooling operation is performed such that the semiconductor substrate is cooled down to 25° C.
19. The method of claim 8 , wherein the capping metallic layer includes TiN doped with Si.
20. The method of claim 16 , wherein the orthorhombic HfZrO 2 contains Ti in an amount of 2-5 mol %.