IP Library Granted Patent US 10,742,350
Granted Patent B2
US 10,742,350 · App. 16/011,021 · Granted Aug 11, 2020

Method and apparatus of rate-matching for communication and broadcasting systems

Inventors: Min Jang (Seongnam-si, KR); Seokki Ahn (Suwon-si, KR); Seho Myung (Seoul, KR); Hongsil Jeong (Suwon-si, KR); Kyungjoong Kim (Suwon-si, KR); Jaeyoel Kim (Seongnam-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H04L1/0013H03M13/13H03M13/6362H04L1/0041H04L1/0057H04L1/0067H04L1/0071
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Quick Facts
Patent No.
US 10,742,350
App. No.
16/011,021
Granted
Aug 11, 2020
Kind
B2
Abstract

A communication method and system for converging a 5th-generation (5G) communication system for supporting higher data rates beyond a 4th-generation (4G) system with a technology for internet of things (IoT) are provided. The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The method and apparatus for polar encoding and rate-matching are disclosed.

Claims (89)

1. A method using a polar code performed by a transmitter in a communication system, the method comprising:

identifying a second bit sequence by encoding a first bit sequence with the polar code, the first bit sequence comprising information to be transmitted;

identifying a plurality of sub-blocks based on the second bit sequence; and

performing an interleaving on the plurality of sub-blocks based on an interleaving pattern,

wherein a number of the plurality of sub-blocks is 32, and

wherein the interleaving pattern is {0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31}.

2. The method of claim 1 , further comprising:

generating a third bit sequence by performing a rate-matching of the interleaved second bit sequence; and

transmitting, to a receiver, the third bit sequence.

3. The method of claim 2 , further comprising:

determining a length of the second bit sequence as a power of 2, based on a length of the first bit sequence and a length of the third bit sequence,

wherein in case that the length of the third bit sequence is shorter than the length of the second bit sequence, one of a puncturing or a shortening is determined to be used for the rate-matching based on a code rate which is determined based on the length of the first bit sequence and the length of the third bit sequence, and

wherein in case that the length of the third bit sequence is longer than the length of the second bit sequence, a repetition is determined to be used for the rate-matching.

4. The method of claim 3 , wherein the identifying of the second bit sequence comprises:

identifying positions of bits to be punctured in case that the puncturing is determined to be used; and

setting the bits to be punctured as 0.

5. The method of claim 3 , wherein the identifying of the second bit sequence comprises:

identifying positions of bits to be shortened in case that the shortening is determined to be used; and

setting the bits to be shortened as 0.

6. The method of claim 3 , wherein in case that the code rate is smaller than a threshold value, the puncturing is determined to be used for the rate-matching.

7. The method of claim 3 , wherein in case that the code rate is greater than a threshold value, the shortening is determined to be used for the rate-matching.

8. The method of claim 3 ,

wherein the generating of the third bit sequence comprises:

storing the interleaved second bit sequence in a circular buffer; and

performing the puncturing of a former portion of bits in the interleaved second bit sequence, in case that the puncturing is determined to be used, and

wherein a length of the former portion of the bits is determined by subtracting the length of the third bit sequence from the length of the second bit sequence.

9. The method of claim 3 ,

wherein the generating of the third bit sequence comprises:

storing the interleaved second bit sequence in a circular buffer; and

performing the shortening of a latter portion of bits of the interleaved second bit sequence, in case that the shortening is determined to be used, and

wherein a length of the latter portion of the bits is determined by subtracting the length of the third bit sequence from the length of the second bit sequence.

10. The method of claim 3 ,

wherein the generating of the third bit sequence comprises:

storing the interleaved second bit sequence in a circular buffer; and

performing the repetition of bits in the interleaved second bit sequence,

in case that the repetition is determined to be used, and

wherein a length of the bits to be repeated is determined by subtracting the length of the second bit sequence from the length of the third bit sequence.

11. An apparatus for transmitting information using a polar code, the apparatus comprising:

a transceiver; and

at least one processor configured to:

identify a second bit sequence by encoding a first bit sequence with the polar code, the first bit sequence comprising information to be transmitted,

divide the second bit sequence into a plurality of sub-blocks,

perform an interleaving on the plurality of sub-blocks of the second bit sequence based on an interleaving pattern,

generate a third bit sequence by performing a rate-matching of the interleaved second bit sequence, and

transmit, to a receiver via the transceiver, the third bit sequence,

wherein a number of the plurality of sub-blocks is 32, and

wherein the interleaving pattern is {0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31}.

12. The apparatus of claim 11 , wherein the at least one processor is further configured to:

generate a third bit sequence by performing a rate-matching of the interleaved second bit sequenced, and

transmit, to a receiver, the third bit sequence.

13. The apparatus of claim 12 , wherein the at least one processor is further configured to determine a length of the second bit sequence as a power of 2, based on a length of the first bit sequence and a length of the third bit sequence,

wherein in case that the length of the third bit sequence is shorter than the length of the second bit sequence, one of a puncturing or a shortening is determined to be used for the rate-matching based on a code rate which is determined based on the length of the first bit sequence and the length of the third bit sequence, and

wherein in case that the length of the third bit sequence is longer than the length of the second bit sequence, a repetition is determined to be used for the rate-matching.

14. The apparatus of claim 13 , wherein, to identify the second bit sequence, the at least one processor is configured to:

identify positions of bits to be punctured in case that the puncturing is determined to be used, and

set the bits to be punctured as 0.

15. The apparatus of claim 13 , wherein, to identify of the second bit sequence, the at least one processor is configured to:

identify positions of bits to be shortened in case that the shortening is determined to be used, and

set the bits to be shortened as 0.

16. The apparatus of claim 13 , wherein in case that the code rate is smaller than a threshold value, the puncturing is determined to be used for the rate-matching.

17. The apparatus of claim 13 , wherein in case that the code rate is greater than a threshold value, the shortening is determined to be used for the rate-matching.

18. The apparatus of claim 13 ,

wherein, to generate the third bit sequence, the at least one processor is further configured to:

store the interleaved second bit sequence in a circular buffer, and

perform the puncturing of a former portion of bits in the interleaved second bit sequence, in case that the puncturing is determined to be used, and

wherein a length of the former portion of the bits is determined by subtracting the length of the third bit sequence from the length of the second bit sequence.

19. The apparatus of claim 13 ,

wherein, to generate the third bit sequence, the at least one processor is further configured to:

store the interleaved second bit sequence in a circular buffer, and

perform the shortening of a latter portion of bits of the interleaved second bit sequence, in case that the shortening is determined to be used, and

wherein a length of the latter portion of the bits is determined by subtracting the length of the third bit sequence from the length of the second bit sequence.

20. The apparatus of claim 13 ,

wherein, to generate of the third bit sequence, the at least one processor is further configured to:

store the interleaved second bit sequence in a circular buffer; and

perform the repetition of bits in the interleaved second bit sequence, in case that the repetition is determined to be used, and

wherein a length of the bits to be repeated is determined by subtracting the length of the second bit sequence from the length of the third bit sequence.

21. A method using a polar code performed by a receiver, the method comprising:

receiving a bit sequence;

de-rate-matching the received bit sequence based on a length of the received bit sequence and a length of information bits;

de-interleaving the de-rate-matched bit sequence based on an interleaving pattern; and

decoding using the polar code on the de-interleaved bit sequence to obtain the information bits,

wherein the interleaving pattern is {0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31}.

22. An apparatus for receiving information using a polar code, the apparatus comprising:

a transceiver; and

at least one processor is configured to:

receive, from a transmitter via the transceiver, a bit sequence, de-rate-match the received bit sequence based on a length of the received bit sequence and a length of information bits,

de-interleave the de-rate-matched bit sequence based on an interleaving pattern, and

decode using the polar code on the de-interleaved bit sequence to obtain the information bits,

wherein the interleaving pattern is {0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31}.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2018
From: JANG, MIN; AHN, SEOKKI; MYUNG, SEHO; JEONG, HONGSIL; KIM, KYUNGJOONG; KIM, JAEYOEL
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 046120/0588 →
Priority Claims (3)
KR 10-2017-0077564 · Jun 19, 2017 · national
KR 10-2017-0097843 · Aug 1, 2017 · national
KR 10-2017-0107573 · Aug 24, 2017 · national
Continuity (1)
Related Publication 20180367239A1 · Dec 20, 2018
Cited By (1)
US 12,418,311