Voltage memory digital pre-distortion circuit

1. An envelope tracking (ET) amplifier circuit comprising:

at least one amplifier circuit configured to amplify a radio frequency (RF) signal based on an ET modulated voltage;

ET tracker circuitry configured to receive an ET modulated target voltage signal comprising a time-variant target voltage envelope and generate the ET modulated voltage comprising a time-variant voltage envelope tracking the time-variant target voltage envelope; and

a voltage input path configured to provide the ET modulated target voltage signal to the ET tracker circuitry, the voltage input path comprising a voltage memory digital pre-distortion (mDPD) circuit configured to:

determine a voltage deviation of the ET modulated voltage relative to the ET modulated target voltage signal as a result of memory nonlinearity of the ET tracker circuitry; and

adjust the time-variant target voltage envelope based on at least one mDPD coefficient to correct the memory nonlinearity to reduce the voltage deviation to a predefined threshold.

2. The ET amplifier circuit of claim 1 , wherein the voltage mDPD circuit is further configured to:

execute an mDPD polynomial in one or more iterations, each selectively configured to extract the at least one mDPD coefficient; and

adjust the time-variant target voltage envelope based on the at least one mDPD coefficient extracted in each of the one or more iterations to reduce the voltage deviation to the predefined threshold.

3. The ET amplifier circuit of claim 2 , wherein the voltage mDPD circuit comprises:

an analog-to-digital converter (ADC) coupled to the ET tracker circuitry;

digital mDPD processor circuitry coupled to the ADC; and

digital voltage adjustment circuitry coupled to the digital mDPD processor circuitry.

4. The ET amplifier circuit of claim 3 , wherein in each of the one or more iterations, the ADC is configured to:

receive an analog voltage feedback signal indicative of the ET modulated voltage in a defined time interval;

convert the analog voltage feedback signal to a digital voltage feedback signal indicative of the ET modulated voltage in the defined time interval; and

provide the digital voltage feedback signal to the digital mDPD processor circuitry.

5. The ET amplifier circuit of claim 4 , wherein the ADC is further configured to receive the analog voltage feedback signal indicative of the ET modulated voltage in each timeslot duration of the RF signal.

6. The ET amplifier circuit of claim 4 , wherein the ADC is further configured to receive the analog voltage feedback signal indicative of the ET modulated voltage in each frame duration of the RF signal.

7. The ET amplifier circuit of claim 4 , wherein in each of the one or more iterations: the digital mDPD processor circuitry is configured to:

determine the voltage deviation of the ET modulated voltage in the defined time interval relative to the ET modulated target voltage signal; execute the mDPD polynomial to extract the at least one mDPD coefficient; and provide the at least one mDPD coefficient to the digital voltage adjustment circuitry; and

the digital voltage adjustment circuitry is configured to generate a digital ET modulated target voltage signal comprising the time-variant target voltage envelope adjusted based on the at least one mDPD coefficient.

8. The ET amplifier circuit of claim 7 , wherein in each of the one or more iterations, the digital mDPD processor circuitry is further configured to compare the voltage deviation to the predefined threshold and terminate the one or more iterations in response to the voltage deviation being equal to or less than the predefined threshold.

9. The ET amplifier circuit of claim 7 , wherein the voltage input path further comprises a digital-to-analog converter (DAC) coupled to the digital voltage adjustment circuitry and configured to convert the digital ET modulated target voltage signal to the ET modulated target voltage signal and provide the ET modulated target voltage signal to the ET tracker circuitry.

10. The ET amplifier circuit of claim 1 , wherein the voltage mDPD circuit is provided in the voltage input path when the RF signal is determined to comprise more than three hundred resource blocks (RBs).

11. The ET amplifier circuit of claim 1 , wherein the voltage mDPD circuit is provided in the voltage input path when the RF signal is determined to have less than three degrees phase variation.

12. The ET amplifier circuit of claim 1 , wherein the voltage mDPD circuit is provided in the voltage input path when the RF signal is determined to comprise more than three hundred resource blocks (RBs) and the RF signal is determined to have less than three degrees phase variation.

13. The ET amplifier circuit of claim 1 , wherein: the at least one amplifier circuit is further configured to receive the RF signal in a carrier frequency at a signal input and output the RF signal in the carrier frequency at a signal output;

the signal output is coupled to frequency-dependent impedance varying in proportion to the carrier frequency of the RF signal; and

the voltage mDPD circuit is provided in the voltage input path when the frequency-dependent impedance coupled to the signal output varies less than twenty percent relative to the carrier frequency.

14. The ET amplifier circuit of claim 1 , wherein the voltage mDPD circuit is provided in the voltage input path when the RF signal is determined to be a Wi-Fi signal transmitted in 80 GHz frequency spectrum.

15. The ET amplifier circuit of claim 1 , further comprising a signal input path coupled to the at least one amplifier circuit and configured to:

receive a digital in-phase (I) signal and a digital quadrature (Q) signal; convert the digital I signal and the digital Q signal to the RF signal; and provide the RF signal to the at least one amplifier circuit.

16. The ET amplifier circuit of claim 15 , wherein the signal input path comprises:

a signal mDPD circuit configured to process the digital I signal and the digital Q signal to suppress non-linear behavior of the at least one amplifier circuit; an I signal digital-to-analog converter (DAC) configured to convert the digital I signal into an analog I signal;

a Q signal DAC configured to convert the digital Q signal into an analog Q signal; and a signal combiner configured to:

combine the analog I signal and the analog Q signal to generate the RF signal; and

provide the RF signal to the at least one amplifier circuit.

17. The ET amplifier circuit of claim 16 , wherein the signal mDPD circuit is provided in the signal input path when the RF signal is determined to comprise more than three hundred resource blocks (RBs).

18. The ET amplifier circuit of claim 16 , wherein the signal mDPD circuit is provided in the signal input path when the RF signal is determined to have more than three degrees phase variation.

19. The ET amplifier circuit of claim 16 , wherein the signal mDPD circuit is provided in the signal input path when the RF signal comprises more than three hundred resource blocks (RBs) and the RF signal has more than three degrees phase variation.