Apparatus of semiconductor memory and method of manufacturing the same

1. A method of manufacturing a semiconductor memory apparatus in which a plurality of memory dies are stacked, the method comprising:

forming a plurality of first memory dies on a wafer;

depositing an under-fill material on the wafer including the plurality of first memory dies formed thereon to form a first part of an under-fill layer, the first part of the under-fill layer including a first portion of the under-fill layer remaining on top surfaces of the plurality of first memory dies;

performing a first half sawing process, the first half sawing process removing the first portion of the under-fill layer, the first half sawing process removing parts of edge portions of the plurality of first memory dies to form first cavities during the removing the first portion of the under-fill layer;

forming a plurality of second memory dies on the plurality of first memory dies;

depositing the under-fill material on the wafer including the plurality of second memory dies formed thereon to form a second part of the under-fill layer on a remaining part of the under-fill layer, the second part of the under-fill layer including a second portion of the under-fill layer remaining on top surfaces of the plurality of second memory dies; and

performing a second half sawing process, the second half sawing process removing the second portion of the under-fill layer, the second half sawing process removing parts of edge portions of the plurality of second memory dies to form second cavities during the removing the second portion of the under-fill layer.

2. The method of claim 1 , wherein

the performing the first half sawing process removes edge portions of four surfaces of each of the plurality of first memory dies by a desired thickness to form the first cavities, and

the performing the second half sawing process removes edge portions of four surfaces of each of the plurality of second memory dies by a desired thickness to form the second cavities.

3. The method of claim 2 , wherein

the performing the first half sawing process forms each of the first cavities such that each of the edge portions of the first memory dies has a thickness of 5 μm or more, and

the performing the second half sawing process forms each of the second cavities such that each of the edge portions of the second memory dies has a thickness of 5 μm or more.

4. The method of claim 2 , wherein

the performing the first half sawing process forms each of the first cavities to have a width that is less than half of a width of each of the first memory dies, and

the performing the second half sawing process forms each of the second cavities to have a width that is less than half of a width of each of the plurality of second memory dies.

5. The method of claim 1 , further comprising:

forming a plurality of third memory dies on the plurality of second memory dies;

depositing the under-fill material on the wafer including the plurality of third memory dies formed thereon to form a third part of the under-fill layer on the remaining part of the under-fill layer, the third part of the under-fill layer including a third portion of the under-filler layer remaining on top surfaces of the plurality of third memory dies; and

performing a third half sawing process, the third half sawing process removing the third portion of the under-fill layer, the third half sawing process removing parts of edge portions of the third memory dies to form third cavities during the removing the third portion of the under-fill layer.

6. The method of claim 5 , wherein the performing the third half sawing process removes edge portions of four surfaces of each of the plurality of third memory dies by a desired thickness to form the third cavities.

7. The method of claim 5 , wherein the performing the third half sawing process forms each of the third cavities such that each of the edge portions of the plurality of third memory dies has a thickness of 5 μm or more.

8. The method of claim 5 , wherein the performing the third half sawing process forms each of the third cavities to have a width that is less than half of a width of each of the plurality of third memory dies.

9. The method of claim 5 , further comprising:

forming a plurality of fourth memory dies on the plurality of third memory dies;

depositing the under-fill material on the wafer including the plurality of fourth memory dies formed thereon to form a fourth part of the under-fill layer on the remaining part of the under-fill layer; and

cutting the wafer along a scribe lane.

10. A method of manufacturing a semiconductor memory apparatus in which a plurality of memory dies are stacked, the method comprising:

forming a plurality of first memory dies on a wafer;

removing parts of edge portions of the plurality of first memory dies to form first cavities;

depositing an under-fill material on the wafer including the plurality of first memory dies formed thereon to form a first part of an under-fill layer;

forming a plurality of second memory dies on the plurality of first memory dies;

removing parts of edge portions of the plurality of second memory dies to form second cavities; and

depositing the under-fill material on the wafer including the plurality of second memory dies formed thereon to form a second part of the under-fill layer.

11. The method of claim 10 , wherein

the removing parts of edge portions of the plurality of first memory dies removes edge portions of four surfaces of each of the plurality of first memory dies by a desired thickness to form the first cavities, and

the removing parts of edge portions of the plurality of second memory dies removes edge portions of four surfaces of each of the plurality of second memory dies by a desired thickness to form the second cavities.

12. The method of claim 10 , wherein

the removing parts of edge portions of the plurality of first memory dies forms each of the first cavities such that each of the edge portions of the first memory dies has a thickness of 5 μm or more, and

the removing parts of edge portions of the plurality of second memory dies forms each of the second cavities such that each of the edge portions of the second memory dies has a thickness of 5 μm or more.

13. The method of claim 10 , wherein

the removing parts of edge portions of the plurality of first memory dies forms each of the first cavities to have a width less than half of a width of each of the plurality of first memory dies, and

the removing parts of edge portions of the plurality of second memory dies forms each of the second cavities to have a width less than half of a width of each of the plurality of second memory dies.

14. The method of claim 10 , further comprising:

forming a plurality of third memory dies on the plurality of second memory dies;

removing parts of edge portions of the plurality of third memory dies to form third cavities; and

depositing the under-fill material on the wafer including the plurality of third memory dies formed thereon to form a third part of the under-fill layer.

15. The method of claim 14 , wherein

the removing parts of the edge portions of the plurality of third memory dies includes removing edge portions of four surfaces of each of the plurality of third memory dies by a desired thickness to form the third cavities.

16. The method of claim 14 , wherein the removing parts of the edge portions of the plurality of third memory dies forms each of the third cavities such that each of the edge portions of the plurality of third memory dies has a thickness of 5 μm or more.

17. The method of claim 14 , wherein the removing parts of the edge portions of the plurality of third memory dies forms each of the third cavities to have a width less than half of a width of each of the plurality of third memory dies.

18. The method of claim 14 , further comprising:

forming a plurality of fourth memory dies on the plurality of third memory dies;

depositing the under-fill material on the wafer including the plurality of fourth memory dies formed thereon to form a fourth part of the under-fill layer; and

cutting the wafer along a scribe lane.

19. A semiconductor memory apparatus comprising:

a first memory die on a substrate, the first memory die including a step between an edge portion and a top surface of the first memory die, the step of the first memory die being defined by a part of the edge portion of the first memory die being removed;

a second memory die on the first memory die, the second memory die including a step between an edge portion and a top surface of the second memory die, the step of the second memory die being defined by a part of the edge portion of the second memory die being removed;

a third memory die on the second memory die, the third memory die including a step between an edge portion and a top surface of the third memory die, the step of the third memory die being defined by a part of the edge portion of the third memory die being removed; and

a fourth memory die on the third memory die.

20. The semiconductor memory apparatus of claim 19 , wherein

the first cavity, second cavity, and third cavity, are respectively defined by edge portions of four surfaces of each of the first memory die, second memory die, and third memory dies being removed by a desired thickness,

each of the edge portions of the first memory die, second memory die, and third memory die has a thickness of 5 μm or more, and

each of the first cavity, second cavity, and third cavity has a width that is less than half of a width of each of the first memory die, second memory die, and third memory die.