IP Library › Granted Patent US 10,749,024
Granted Patent B2
US 10,749,024 · App. 16/110,332 · Granted Aug 18, 2020

Semiconductor device

Inventor: Akihiro Tanaka (Himeji Hyogo, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H01L29/7813H01L27/0207H01L27/088H01L29/0696H01L29/41741H01L29/4236H01L29/4238
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Quick Facts
Patent No.
US 10,749,024
App. No.
16/110,332
Granted
Aug 18, 2020
Kind
B2
Abstract

A semiconductor device of an embodiment includes a first region including a first portion of a semiconductor layer having first and second planes, a first trench, a first gate electrode, a first source electrode and a drain electrode; a second region adjacent to the first region in a first direction and including a second portion of the semiconductor layer, a second trench, a second gate electrode, a second source electrode on the first plane side, and the drain electrode; a third region adjacent to the first region in a second direction crossing the first direction and including a third portion of the semiconductor layer, a third trench, a third gate electrode, a third source electrode on the first plane side, and the drain electrode; a first gate electrode pad connected to the first gate electrode; and a second gate electrode pad connected to the second and third gate electrodes.

Claims (27)

1. A semiconductor device comprising:

a first region including a first portion of a semiconductor layer having a first plane and a second plane, a first trench provided in the first portion, a first gate electrode provided in the first trench, a first source electrode provided on a first plane side of the first portion, and a drain electrode provided on a second plane side of the first portion;

a second region provided to be adjacent to the first region in a first direction and including a second portion of the semiconductor layer, a second trench provided in the second portion, a second gate electrode provided in the second trench, a second source electrode provided on the first plane side of the second portion, and the drain electrode provided on the second plane side of the second portion;

a third region provided to be adjacent to the first region in a second direction crossing the first direction and including a third portion of the semiconductor layer, a third trench provided in the third portion, a third gate electrode provided in the third trench, a third source electrode provided on the first plane side of the third portion, and the drain electrode provided on the second plane side of the third portion;

a first gate electrode pad electrically connected to the first gate electrode; and

a second gate electrode pad electrically connected to the second gate electrode and the third gate electrode,

wherein a first side of the first region opposing the second region has a first length and a second side of the first region opposing the third region has a second length different from the first length.

2. The semiconductor device according to claim 1 , wherein the first direction and the second direction are orthogonal to each other.

3. The semiconductor device according to claim 1 , wherein

the first side is parallel to the extending direction of the first trench.

4. The semiconductor device according to claim 3 , wherein the first length is longer than the second length.

5. The semiconductor device according to claim 1 , wherein the second source electrode and the third source electrode are electrically connected.

6. The semiconductor device according to claim 1 , further comprising

a fourth portion provided to be adjacent to the first region in a third direction different from the first direction and the second direction and including a fourth portion of the semiconductor layer, a fourth trench provided in the fourth portion, a fourth gate electrode provided in the fourth trench, a fourth source electrode in contact with the first plane of the fourth portion, and the drain electrode provided on the second plane side of the fourth portion.

7. The semiconductor device according to claim 6 , wherein the first direction and the second direction are orthogonal to each other, and the first direction and the third direction are orthogonal to each other.

8. The semiconductor device according to claim 6 , wherein the second source electrode, the third source electrode, and the fourth source electrode are electrically connected.

9. The semiconductor device according to claim 1 , wherein

the second side is parallel to the extending direction of the first trench.

10. The semiconductor device according to claim 9 , wherein the first length is longer than the second length.

11. The semiconductor device according to claim 1 , wherein the semiconductor layer is silicon.

12. A semiconductor device comprising:

a first region including a first portion of a semiconductor layer having a first plane and a second plane, a first trench provided in the first portion, a first gate electrode provided in the first trench, a first source electrode provided on a first plane side of the first portion, and a drain electrode provided on a second plane side of the first portion;

a second region provided to be adjacent to the first region in a first direction and including a second portion of the semiconductor layer, a second trench provided in the second portion, a second gate electrode provided in the second trench, a second source electrode provided on the first plane side of the second portion, and the drain electrode provided on the second plane side of the second portion;

a third region provided to be adjacent to the first region in a second direction crossing the first direction and including a third portion of the semiconductor layer, a third trench provided in the third portion, a third gate electrode provided in the third trench, a third source electrode provided on the first plane side of the third portion, and the drain electrode provided on the second plane side of the third portion;

a first gate electrode pad electrically connected to the first gate electrode; and

a second gate electrode pad electrically connected to the second gate electrode and the third gate electrode,

wherein an angle between a first side of the first region opposing the second region and a second side of the first region opposing the third region is smaller than 90 degrees.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2018
From: TANAKA, AKIHIRO
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 046698/0966 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2018
From: TANAKA, AKIHIRO
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICE & STORAGE CORPORATION
Reel/Frame 046683/0114 →
Priority Claims (1)
JP 2018-053682 · Mar 21, 2018 · national
Continuity (1)
Related Publication 20190296148A1 · Sep 26, 2019