IP Library › Granted Patent US 10,749,025
Granted Patent B2
US 10,749,025 · App. 16/114,174 · Granted Aug 18, 2020

Semiconductor device and manufacturing method thereof

Inventor: Tatsuya Naito (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L29/7813H01L29/0696H01L29/083H01L29/0834H01L29/1095H01L29/407H01L29/417H01L29/456H01L29/66348H01L29/66545H01L29/739H01L29/7396H01L29/7397H01L29/861H01L29/868
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Quick Facts
Patent No.
US 10,749,025
App. No.
16/114,174
Granted
Aug 18, 2020
Kind
B2
Abstract

A semiconductor device having a contact trench is provided. The semiconductor device including: a semiconductor substrate; a drift region of the first conductivity type provided on an upper surface side of the semiconductor substrate; a base region of the second conductivity type provided above the drift region; a source region of the first conductivity type provided above the base region; two or more trench portions provided penetrating through the source region and the base region from an upper end side of the source region; a contact trench provided in direct contact with the source region between adjacent trench portions; and a contact layer of the second conductivity type provided below the contact trench, is provided. A peak of a doping concentration of the contact layer is positioned shallower than a position of a lower end of the source region.

Claims (69)

1. A semiconductor device comprising:

a semiconductor substrate;

a drift region of a first conductivity type provided on an upper surface side of the semiconductor substrate;

a base region of a second conductivity type provided above the drift region;

a source region of a first conductivity type provided above the base region;

two or more trench portions provided penetrating through the source region and the base region from an upper end side of the source region;

a contact trench provided in direct contact with the source region between adjacent trench portions;

a first contact layer of a second conductivity type provided below the contact trench, wherein

a peak of a doping concentration of the first contact layer is positioned shallower than a position of a lower end of the source region, and

a lower end of the first contact layer is positioned deeper than the position of the lower end of the source region; and

a contact region of a second conductivity type provided above the base region, wherein

the source region and the contact region are alternately provided in an extending direction of the trench portions.

2. A semiconductor device comprising:

a semiconductor substrate;

a drift region of a first conductivity type provided on an upper surface side of the semiconductor substrate;

a base region of a second conductivity type provided above the drift region;

a source region of a first conductivity type provided above the base region;

two or more trench portions provided penetrating through the source region and the base region from an upper end side of the source region;

a contact trench provided in direct contact with the source region between adjacent trench portions; and

a first contact layer of a second conductivity type provided below the contact trench, wherein

a peak of a doping concentration of the first contact layer is positioned shallower than a position of a lower end of the source region, and

a lower end of the first contact layer is positioned deeper than the position of the lower end of the source region;

wherein the doping concentration of the first contact layer is larger than a doping concentration of the source region at a same depth below the contact trench.

3. The semiconductor device according to claim 2 , wherein the first contact layer has a plurality of peaks of a doping concentration.

4. The semiconductor device according to claim 3 , wherein the peak position is a peak position of a peak having a maximum doping concentration among the plurality of peaks.

5. The semiconductor device according to claim 2 , wherein the lower end of the source region is positioned deeper than a position of a lower end of the contact trench.

6. The semiconductor device according to claim 2 , wherein

each of the two or more trench portions have a trench conductive portion, and

the lower end of the source region is positioned deeper than a position of an upper end of the trench conductive portion.

7. The semiconductor device according to claim 2 , wherein the lower end of the source region has a width from 10% to 30% inclusive of a mesa width between the two or more trench portions, in an arrangement direction of the trench portions.

8. The semiconductor device according to claim 2 , wherein the source region is provided extending in an extending direction of the trench portions.

9. The semiconductor device according to claim 2 , wherein the first contact layer is provided extending in an extending direction of the two or more trench portions.

10. The semiconductor device according to claim 2 , wherein the first contact layer is provided at least a part of a side wall of the contact trench.

11. The semiconductor device according to claim 2 , wherein a thickness of the first contact layer in a depth direction is from 0.1 μm to 1.0 μm inclusive.

12. The semiconductor device according to claim 2 , wherein the lower end of the first contact layer is positioned shallower than a position half a thickness of the base region.

13. The semiconductor device according to claim 2 , wherein the lower end of the first contact layer is at a position as deep as a position of a lower end of the base region.

14. The semiconductor device according to claim 2 , wherein an upper end of the first contact layer is positioned shallower than a position of the lower end of the source region.

15. The semiconductor device according to claim 2 , wherein a width of the lower end of the first contact layer is narrower than a width of an upper end of the first contact layer in an arrangement direction of the trench portions.

16. The semiconductor device according to claim 2 , wherein a lower end of the contact trench has a width from 0.1 μm to 0.4 μm inclusive, in an arrangement direction of the trench portions.

17. The semiconductor device according to claim 2 , wherein the contact trench is tapered.

18. The semiconductor device according to claim 2 , further comprising:

a first accumulation region of a first conductivity type provided between the drift region and the base region, wherein

the first accumulation region has a concentration higher than a concentration of the drift region.

19. The semiconductor device according to claim 18 , wherein the first contact layer is in direct contact with the first accumulation region.

20. The semiconductor device according to claim 18 , wherein the lower end of the first contact layer is provided at a position deeper than half a distance between an upper end of the first accumulation region and the lower end of the source region.

21. The semiconductor device according to claim 18 , further comprising:

a second accumulation region of a first conductivity type formed at a position deeper than a position of the first accumulation region, wherein

the second accumulation region has a doping concentration higher than a doping concentration of the drift region.

22. A semiconductor device comprising:

a semiconductor substrate;

a drift region of a first conductivity type provided on an upper surface side of the semiconductor substrate;

a base region of a second conductivity type provided above the drift region;

a source region of a first conductivity type provided above the base region;

two or more trench portions provided penetrating through the source region and the base region from an upper end side of the source region;

a contact trench provided in direct contact with the source region between adjacent trench portions; and

a first contact layer of a second conductivity type provided below the contact trench, wherein

a peak of a doping concentration of the first contact layer is positioned shallower than a position of a lower end of the source region, and

a lower end of the first contact layer is positioned deeper than the position of the lower end of the source region; and

a second contact layer of a second conductivity type provided below the first contact layer.

23. A manufacturing method of a semiconductor device comprising:

forming a drift region of a first conductivity type, a base region of a second conductivity type, a source region of a first conductivity type, two or more trench portions penetrating through the source region and the base region, on an upper surface side of a semiconductor substrate;

forming a contact trench between two trench portions so as to be in direct contact with the source region; and

forming a contact layer of a second conductivity type by implanting dopants below the base region from a lower end of the contact trench, such that a peak of a doping concentration is positioned shallower than a position of a lower end of the source region, in a region facing the lower end of the contact trench, wherein

a lower end of the contact layer is positioned deeper than the position of the lower end of the source region;

wherein the doping concentration of the first contact layer is larger than a doping concentration of the source region at a same depth below the contact trench.

24. The manufacturing method of the semiconductor device according to claim 23 , wherein the forming the contact layer includes implanting a first dopant and implanting a second dopant.

25. The manufacturing method of the semiconductor device according to claim 23 , wherein

the forming the source region includes forming the source region in an entire surface of the base region, and

the forming the contact trench includes forming the contact trench between the two trench portions inside the source region formed in the entire surface of the base region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2018
From: NAITO, TATSUYA
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 046731/0545 →
Priority Claims (2)
JP 2016-180025 · Sep 14, 2016 · national
JP 2017-154304 · Aug 9, 2017 · national
Continuity (2)
Continuation PCTJP2017033361 · Sep 14, 2017
Related Publication 20180374948A1 · Dec 27, 2018