Semiconductor device and method for manufacturing semiconductor device
View Patent ↗Disclosed is a semiconductor device including: an insulating layer; a source electrode and a drain electrode embedded in the insulating layer; an oxide semiconductor layer in contact and over the insulating layer, the source electrode, and the drain electrode; a gate insulating layer over and covering the oxide semiconductor layer; and a gate electrode over the gate insulating layer, where the upper surfaces of the insulating layer, the source electrode, and the drain electrode exist coplanarly. The upper surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less, and the difference in height between the upper surface of the insulating layer and the upper surface of the source electrode or the drain electrode is less than 5 nm. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.
1. A semiconductor device comprising:
a substrate;
an insulating layer over the substrate; and
a transistor comprising:
an intrinsic oxide semiconductor layer including a channel formation region;
a gate insulating layer over the intrinsic oxide semiconductor layer;
a gate electrode over the gate insulating layer, and
a source electrode and a drain electrode each electrically connected to the intrinsic oxide semiconductor layer,
wherein the intrinsic oxide semiconductor layer is in contact with a top surface of the insulating layer,
wherein the channel formation region overlaps with a region of the top surface of the insulating layer,
wherein the region of the top surface of the insulating layer has a root-mean- square roughness of 1 nm or less,
wherein a first edge side of the gate electrode overlaps with an edge side of the source electrode,
wherein a second edge side of the gate electrode, which is opposed to the first edge side of the gate electrode, overlaps with an edge side of the drain electrode,
wherein the edge side of the source electrode is opposed to the edge side of the drain electrode, and
wherein a carrier density of the intrinsic oxide semiconductor layer is less than 1×10 12 /cm 3 .
2. The semiconductor device according to claim 1 , wherein the intrinsic oxide semiconductor layer comprises at least one of In, Ga, Sn, and Zn.
3. The semiconductor device according to claim 1 , wherein an off-state current per a channel width of the transistor is equal to or less than 100 zA/μm.