IP Library › Granted Patent US 10,755,860
Granted Patent B2
US 10,755,860 · App. 16/274,636 · Granted Aug 25, 2020

Multilayer ceramic electronic component

Inventors: Kyeong Jun Kim (Suwon-si, KR); Jang Hyun Lee (Suwon-si, KR); Hae Suk Chung (Suwon-si, KR); Do Lee (Suwon-si, KR); Byung Sung Kang (Suwon-si, KR); Ho In Jun (Suwon-si, KR)
Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
H01G4/30H01G4/012H01G4/1227H01G4/232
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Quick Facts
Patent No.
US 10,755,860
App. No.
16/274,636
Granted
Aug 25, 2020
Kind
B2
Abstract

A multilayer ceramic electronic component includes: a ceramic body having a dielectric layer, and a plurality of first and second internal electrodes facing each other with the dielectric layer interposed therebetween; and first and second external electrodes disposed on an outer surface of the ceramic body, respectively. The ceramic body includes an active portion including a plurality of internal electrodes facing each other with the dielectric layer interposed therebetween to form capacitance, and cover portions formed on upper and lower portions of the active portion. A buffer region is disposed between at least one pair of first and second internal electrodes among the plurality of first and second internal electrodes disposed inside the active portion, and satisfies the relation 0<tb<150 μm+td, where td is a thickness of the dielectric layer, and tb is a thickness of the buffer region.

Claims (22)

1. A multilayer ceramic electronic component comprising:

a ceramic body including a plurality of dielectric layers and a plurality of first and second internal electrodes facing each other with the plurality of dielectric layers interposed therebetween, respectively, and having first and second surfaces facing each other in a stacking direction, third and fourth surfaces connected to the first and second surfaces and facing each other in a length direction, and fifth and sixth surfaces connected to the first to fourth surfaces and facing each other in a width direction; and

first and second external electrodes disposed on the third and fourth surfaces of the ceramic body, respectively, and electrically connected to the plurality of first and second internal electrodes, respectively,

wherein the ceramic body includes an active portion including the plurality of first and second internal electrodes, and cover portions disposed on upper and lower surfaces of the active portion in the stacking direction,

wherein a buffer region is disposed between at least one pair of first and second internal electrodes among the plurality of first and second internal electrodes disposed inside the active portion,

wherein at least one dielectric layer among the plurality of dielectric layers is disposed on an upper or lower surface of the buffer region and is in direct contact with the buffer region,

wherein a dielectric material of the buffer region is different from a dielectric material of the dielectric layer,

wherein a thickness of the buffer region satisfies the relation of 0<tb<150 μm+td, where a thickness of each dielectric layer is denoted by “td”, and the thickness of the buffer region is denoted by “tb”,

wherein the thickness td of each dielectric layer is 1.2 μm or more and less than 2.8 μm, and

wherein a thickness of each of the plurality of first and second internal electrodes is denoted by “te”, and td>2 ×te.

2. The multilayer ceramic electronic component of claim 1 , wherein the thickness of the buffer region satisfies the relation of 0<tb<100 μm+td.

3. The multilayer ceramic electronic component of claim 1 , wherein the buffer region is disposed in a center portion of the ceramic body as a single layer.

4. The multilayer ceramic electronic component of claim 1 , wherein the buffer region is disposed in plural inside the active portion.

5. The multilayer ceramic electronic component of claim 1 , wherein a thickness of each of the plurality of first and second internal electrodes is denoted by “te”, and te is less than 1 μm.

6. The multilayer ceramic electronic component of claim 5 , wherein the thickness te of each of the plurality of first and second internal electrodes is 0.2 μm or more.

7. The multilayer ceramic electronic component of claim 1 , wherein each of the first and second external electrodes includes an electrode layer electrically connected to the plurality of first or second internal electrodes, and a conductive resin layer disposed on the electrode layer, and

the electrode layer and the conductive resin layer are each extend in the length direction on the first and second surfaces of the ceramic body.

8. The multilayer ceramic electronic component of claim 7 , wherein a length of an extending portion of the electrode layer, measured from a corner edge of the electrode layer close to the third or fourth surface to an end of the extending portion of the electrode layer extending on the respective first or second surface, is smaller than a length of an extending portion of the conductive resin layer, measured from a corner edge of the conductive resin layer close to the third or fourth surface to an end of the extending portion of the conductive resin layer extending on the respective first or second surface.

9. The multilayer ceramic electronic component of claim 7 , wherein the electrode layer includes at least one conductive metal selected from the group consisting of copper (Cu), silver (Ag), nickel (Ni), and alloys thereof.

10. The multilayer ceramic electronic component of claim 7 , wherein the conductive resin layer includes a base resin and at least one conductive metal selected from the group consisting of copper (Cu), silver (Ag), nickel (Ni), and alloys thereof.

11. The multilayer ceramic electronic component of claim 1 , wherein the active portion is divided by a plurality of pairs comprising one first internal electrode and one second internal electrode, and the buffer region is disposed between a first pair of the plurality of pairs and a second pair adjacent to the first pair.

12. The multilayer ceramic electronic component of claim 11 , wherein one surface of the buffer region is in contact with one second internal electrode of the second pair, and another surface of the buffer region is spaced apart from the one first internal electrode of the first pair.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S DATA PREVIOUSLY RECORDED ON REEL 048323 FRAME 0343. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 2, 2019
From: KIM, KYEONG JUN; LEE, JANG HYUN; CHUNG, HAE SUK; LEE, DO; KANG, BYUNG SUNG; JUN, HO IN
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 049079/0897 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2019
From: KIM, KYEONG JUN; LEE, JANG HYUN; CHUNG, HAE SUK; LEE, DO
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 048323/0343 →
Priority Claims (1)
KR 10-2018-0137296 · Nov 9, 2018 · national
Continuity (1)
Related Publication 20200152389A1 · May 14, 2020