Shared contact structure and methods for forming the same
View Patent ↗A butted contact structure is provided. In one embodiment, a structure includes a first transistor on a substrate, the first transistor comprising a first source or drain region, a first gate, and a first gate spacer being disposed between the first gate and the first source or drain region. The structure includes a second transistor on the substrate, the second transistor comprising a second source or drain region, a second gate, and a second gate spacer being disposed between the second gate and the second source or drain region. The structure includes a butted contact disposed above and extending from the first source or drain region to at least one of the first or second gate, a portion of the first gate spacer extending a distance into the butted contact to separate a first bottom surface of the butted contact from a second bottom surface of the butted contact.
1. A structure comprising:
a first transistor on a substrate, the first transistor comprising a first source or drain region, a first gate, and a first gate spacer being disposed between the first gate and the first source or drain region;
a second transistor on the substrate, the second transistor comprising a second source or drain region, a second gate, and a second gate spacer being disposed between the second gate and the second source or drain region; and
a butted contact disposed above and extending from the first source or drain region to at least one of the first gate or the second gate, a portion of the first gate spacer extending a distance into the butted contact to separate a first bottom surface of the butted contact from a second bottom surface of the butted contact.
2. The structure of claim 1 , wherein the portion of the first gate spacer has a tapered profile.
3. The structure of claim 1 , wherein the portion of the first gate spacer has a first sidewall and a second sidewall intersecting the first sidewall.
4. The structure of claim 3 , wherein the first sidewall contacts the first bottom surface of the butted contact at an angle in a range of 91° to 100°.
5. The structure of claim 3 , wherein the first bottom surface and the second bottom surface are at a same elevation.
6. The structure of claim 3 , wherein the first bottom surface and the second bottom surface are at different elevations.
7. The structure of claim 1 , wherein a ratio of a width of the butted contact at the first source or drain region to a width of the butted contact along an upper surface of the butted contact is in a range from about 1:1.5 to about 1:3.
8. A structure comprising:
a first transistor on a substrate, the first transistor comprising a source or drain region;
a conductive feature contacting the source or drain region;
a gate electrode of a gate structure of a second transistor on the substrate;
a butted contact comprising (i) a first surface contacting the gate electrode, (ii) a second surface contacting the conductive feature, (iii) a third surface extending at a first angle from the first surface, and (iv) a fourth surface extending at a second angle from the second surface, the third surface intersecting the fourth surface at a third angle; and
a gate spacer disposed between the source or drain region and the gate structure, a portion of the gate spacer being disposed laterally between the third surface and the fourth surface.
9. The structure of claim 8 , wherein the first surface and the second surface are co-planar.
10. The structure of claim 8 , wherein the first surface and the second surface are at different elevations.
11. The structure of claim 8 , wherein the first angle is in a range from 91° to 100°, the second angle is in a range from 91° to 100°, and the third angle is greater than 0°.
12. The structure of claim 8 , wherein the portion of the gate spacer has a tapered profile.
13. The structure of claim 8 , wherein the butted contact comprises tungsten, cobalt, copper, ruthenium, aluminum, gold, silver, an alloy thereof, or a combination thereof.
14. The structure of claim 8 , wherein a vertical distance between the first surface and the second surface is less than about 5 nm.
15. A structure comprising:
an active area in a substrate;
a conductive feature over the active area;
a gate structure over the substrate, the gate structure comprising a gate spacer and a gate electrode, wherein the gate spacer is interposed between the gate electrode and the conductive feature; and
a butted contact contacting the conductive feature and the gate electrode, wherein an upper surface of the gate spacer is higher than a first interface between the gate electrode and the butted contact, wherein the upper surface of the gate spacer is higher than a second interface between the conductive feature and the butted contact.
16. The structure of claim 15 , wherein the gate spacer has angled sidewalls that intersect at an angle between about 2° to about 20°.
17. The structure of claim 15 further comprising a silicide region interposed between the conductive feature and the active area.
18. The structure of claim 15 further comprising an interlayer dielectric layer over the substrate, wherein a first portion of the interlayer dielectric layer is interposed between the gate spacer and the conductive feature.
19. The structure of claim 18 , wherein the gate spacer protrudes above the first portion of the interlayer dielectric layer.
20. The structure of claim 15 , wherein the first interface is non-planar with the second interface.