Thin-film transistor substrate and display device including the same
A thin-film transistor substrate may include a substrate, a transistor on the substrate, and including an active pattern, and a gate electrode insulated from the active pattern, and a first protection member on the transistor, and overlapping the transistor in a plan view.
1. A thin-film transistor substrate, comprising:
a substrate;
a transistor on the substrate, and comprising:
an active pattern comprising a channel region; and
a gate electrode insulated from the active pattern;
a data line and a driving voltage line above the gate electrode for respectively transmitting a data signal and a driving voltage;
a first protection member on the transistor, and overlapping the transistor in a plan view, the first protection member being on a same level as and protruding and extending away from one of the data line and the driving voltage line in a plan view; and
a first planarization layer surrounding sides of the first protection member, and having an elastic modulus lower than that of the first protection member,
wherein the first protection member is on the channel region to correspond to the channel region in a plan view.
2. The thin-film transistor substrate of claim 1 , wherein the active pattern further comprises a source region, and a drain region.
3. The thin-film transistor substrate of claim 1 , wherein the first protection member comprises one of a metal and an inorganic insulating material.
4. The thin-film transistor substrate of claim 1 , wherein the first protection member is on a same level as the data line and the driving voltage line, and
wherein the first protection member protrudes from one of the data line and the driving voltage line.
5. The thin-film transistor substrate of claim 1 , wherein the first protection member is in contact with an upper portion or a lower portion of one of the data line and the driving voltage line.
6. The thin-film transistor substrate of claim 1 , further comprising a second protection member on the first planarization layer and overlapping the transistor in a plan view.
7. The thin-film transistor substrate of claim 6 , further comprising a second planarization layer on the second protection member,
wherein an elastic modulus of the second protection member is greater than an elastic modulus of the second planarization layer.
8. The thin-film transistor substrate of claim 6 , wherein the second protection member comprises one of a metal and an inorganic insulating material.
9. The thin-film transistor substrate of claim 1 , wherein the first planarization layer comprises an organic insulating material.
10. The thin-film transistor substrate of claim 1 , wherein the substrate comprises:
a first flexible layer; and
a second flexible layer on the first flexible layer,
wherein the thin-film transistor substrate further comprises a second protection member between the first flexible layer and the second flexible layer, and overlapping the transistor in a plan view.
11. The thin-film transistor substrate of claim 10 , wherein an elastic modulus of the second protection member is greater than an elastic modulus of the second flexible layer.
12. The thin-film transistor substrate of claim 1 , further comprising:
a buffer layer between the substrate and the active pattern; and
a second protection member between the substrate and the buffer layer, the second protection member overlapping the transistor in a plan view.
13. The thin-film transistor substrate of claim 12 , wherein an elastic modulus of the second protection member is greater than an elastic modulus of the buffer layer.
14. A display device, comprising:
a substrate;
a scan line on the substrate for transmitting a scan signal;
a data line and a driving voltage line crossing the scan line for respectively transmitting a data signal and a driving voltage;
a first transistor coupled to the scan line and the data line, and comprising a first active pattern, and a first gate electrode insulated from the first active pattern;
a second transistor coupled to the first transistor, and comprising a second active pattern, and a second gate electrode insulated from the second active pattern;
a first protection member on the first transistor, and overlapping the first transistor in a plan view, the first protection member being on a same level as and protruding and extending away from one of the data line and the driving voltage line in a plan view;
a first planarization layer surrounding sides of the first protection member, and having an elastic modulus lower than that of the first protection member; and
a light emitting element coupled to the second transistor,
wherein the first active pattern comprises a first channel region, and
wherein the first protection member is on the first channel region to correspond to the first channel region in a plan view.
15. The display device of claim 14 , wherein the first active pattern further comprises a first source region, and a first drain region.
16. The display device of claim 14 , further comprising a second protection member on the first protection member, and overlapping the first transistor in a plan view.
17. The display device of claim 14 , further comprising a second protection member inside the substrate, or between the substrate and the first transistor, the second protection member overlapping the first transistor in a plan view.