Semiconductor device

1. A semiconductor device, comprising:

a first electrode;

a first semiconductor region provided on the first electrode and electrically connected to the first electrode, the first semiconductor region being of a first conductivity type;

a second semiconductor region electrically connected to the first electrode and provided around the first semiconductor region along a first plane crossing a first direction, the first direction being from the first electrode toward the first semiconductor region, the second semiconductor region being of a second conductivity type;

a third semiconductor region provided on the first semiconductor region and the second semiconductor region, the third semiconductor region being of the first conductivity type, an impurity concentration of the first conductivity type in the third semiconductor region being lower than an impurity concentration of the first conductivity type in the first semiconductor region;

a fourth semiconductor region provided on a portion of the third semiconductor region, the fourth semiconductor region being of the second conductivity type, an impurity concentration of the second conductivity type in the fourth semiconductor region being lower than an impurity concentration of the second conductivity type in the second semiconductor region;

a fifth semiconductor region provided selectively on the fourth semiconductor region, the fifth semiconductor region being of the first conductivity type;

a gate electrode opposing, in a second direction with a gate insulating layer interposed, the fifth semiconductor region, the fourth semiconductor region, and the portion of the third semiconductor region, the second direction being perpendicular to the first direction;

a sixth semiconductor region provided on another portion of the third semiconductor region, the sixth semiconductor region being of the second conductivity type, an impurity concentration of the second conductivity type in the sixth semiconductor region being higher than the impurity concentration of the second conductivity type in the fourth semiconductor region;

a second electrode provided on the fourth semiconductor region and the fifth semiconductor region and electrically connected to the fourth semiconductor region, the fifth semiconductor region, and the sixth semiconductor region; and

an interconnect portion electrically connected to the gate electrode, separated from the second electrode, and provided on the sixth semiconductor region with an insulating layer interposed,

a proportion of a surface area along the first plane of the first semiconductor region positioned under the sixth semiconductor region to a surface area along the first plane of the second semiconductor region positioned under the sixth semiconductor region being smaller than a proportion of a surface area along the first plane of the first semiconductor region positioned under the fourth semiconductor region to a surface area along the first plane of the second semiconductor region positioned under the fourth semiconductor region.

2. The device according to claim 1 , wherein

the sixth semiconductor region is arranged with the gate electrode in a third direction perpendicular to the first direction and the second direction, and

a lower end of the sixth semiconductor region is positioned lower than a lower end of the gate electrode and overlaps, in the first direction with the gate insulating layer interposed, an end portion in the third direction of the gate electrode.

3. The device according to claim 1 , wherein the first semiconductor region is not provided under the sixth semiconductor region.

4. The device according to claim 1 , wherein

the fourth semiconductor region and the gate electrode are provided alternately in the second direction,

one or more of the fifth semiconductor regions is selectively provided on each of a plurality of the fourth semiconductor regions,

a plurality of the first semiconductor regions is provided to be separated from each other, and

a proportion of a surface area along the first plane of the plurality of first semiconductor regions positioned under the sixth semiconductor region to the surface area along the first plane of the second semiconductor region positioned under the sixth semiconductor region is smaller than a proportion of a surface area along the first plane of the plurality of first semiconductor regions positioned under the plurality of fourth semiconductor regions to a surface area along the first plane of the second semiconductor region positioned under the plurality of fourth semiconductor regions.

5. The device according to claim 4 , wherein the sixth semiconductor region is provided around the plurality of fourth semiconductor regions and the plurality of gate electrodes along the first plane.

6. The device according to claim 1 , wherein

the first semiconductor region and a portion of the second semiconductor region are provided alternately in a third direction perpendicular to the first direction and the second direction, and

each of a plurality of the first semiconductor regions extends in the second direction.

7. The device according to claim 1 , comprising a cell region including the first semiconductor region, a portion of the second semiconductor region, the portion of the third semiconductor region, the fourth semiconductor region, the fifth semiconductor region, and the second electrode,

a plurality of the cell regions being provided to be separated from each other in a third direction perpendicular to the first direction and the second direction,

in each of the plurality of cell regions, a plurality of the first semiconductor regions being provided to be separated from each other in the second direction and the third direction, each of the plurality of first semiconductor regions extending in the second direction,

the second semiconductor region including a trigger region,

a portion of the trigger region being provided in one of the plurality of cell regions and positioned between a portion of the plurality of first semiconductor regions of the one of the plurality of cell regions and another portion of the plurality of first semiconductor regions of the one of the plurality of cell regions in the second direction,

another portion of the trigger region being provided in another one of the plurality of cell regions and positioned between a portion of the plurality of first semiconductor regions of the other one of the plurality of cell regions and another portion of the plurality of first semiconductor regions of the other one of the plurality of cell regions in the second direction, the other one of the plurality of cell regions being adjacent to the one of the plurality of cell regions in the third direction,

a length in the second direction of the trigger region and a length in the third direction of the trigger region being longer than a distance in the third direction between the first semiconductor regions adjacent to each other in the third direction in the one of the plurality of cell regions.