Granted Patent B2

US 12,550,398 · App. 18/177,888 · Granted Feb 10, 2026

Inventors: Teruyuki Ohashi (Kawasaki Kanagawa, JP); Hiroshi Kono (Himeji Hyogo, JP); Shunsuke Asaba (Himeji Hyogo, JP); Takahiro Ogata (Kawasaki Kanagawa, JP)

Assignee: KABUSHIKI KAISHA TOSHIBA

H10D62/8325H10D8/60H10D62/106H10D84/146

Abstract

Claims (65)

1 . A semiconductor device comprising:

a semiconductor chip including a plurality of transistor regions and at least one diode region,

wherein the transistor regions include:

a silicon carbide layer having a first plane and a second plane facing the first plane, the silicon carbide layer including a first silicon carbide region of n-type having a plurality of first portions in contact with the first plane, a second silicon carbide region of p-type provided between the first silicon carbide region and the first plane, and a third silicon carbide region of n-type provided between the second silicon carbide region and the first plane;

a first electrode in contact with the first portions, the second silicon carbide region, and the third silicon carbide region;

a second electrode in contact with the second plane;

a gate electrode facing the second silicon carbide region; and

a gate insulating layer provided between the gate electrode and the second silicon carbide region,

wherein the at least one diode region includes:

the silicon carbide layer including the first silicon carbide region of n-type having a plurality of second portions in contact with the first plane and a fourth silicon carbide region of p-type provided between the first silicon carbide region and the first plane;

the first electrode in contact with the second portions and the fourth silicon carbide region; and

the second electrode,

wherein an occupied area per unit area of the fourth silicon carbide region projected onto the first plane is larger than an occupied area per the unit area of the second silicon carbide region projected onto the first plane,

wherein a first diode region being one of the at least one diode region is provided between a first transistor region and a second transistor region, the first transistor region is one of the transistor regions, the second transistor region is one of the transistor regions provided in a first direction with respect to the first transistor region, and

wherein the first transistor region includes a third electrode provided on a side of the first plane of the silicon carbide layer and separated from the first electrode;

a first conductor having one end in contact with the first electrode and applying a voltage to the first electrode;

a second conductor having one end in contact with the third electrode and applying a voltage to the third electrode;

a first metal layer configured to face the second electrode and electrically connected to the second electrode;

a second metal layer in contact with the other end of the first conductor; and

a third metal layer in contact with the other end of the second conductor.

2 . The semiconductor device according to claim 1 , wherein the third electrode is in contact with the first portions, the second silicon carbide region, and the third silicon carbide region.

3 . The semiconductor device according to claim 1 , wherein a distance between the third electrode and the at least one diode region is 100 μm or less.

4 . A semiconductor device comprising:

a semiconductor chip including a plurality of transistor regions and at least one diode region,

wherein the transistor regions include:

a silicon carbide layer having a first plane and a second plane facing the first plane, the silicon carbide layer including a first silicon carbide region of n-type having a plurality of first portions in contact with the first plane, a second silicon carbide region of p-type provided between the first silicon carbide region and the first plane, and a third silicon carbide region of n-type provided between the second silicon carbide region and the first plane;

a first electrode in contact with the first portions, the second silicon carbide region, and the third silicon carbide region;

a second electrode in contact with the second plane;

a gate electrode facing the second silicon carbide region; and

a gate insulating layer provided between the gate electrode and the second silicon carbide region,

wherein the at least one diode region includes:

the silicon carbide layer including the first silicon carbide region of n-type having a plurality of second portions in contact with the first plane and a fourth silicon carbide region of p-type provided between the first silicon carbide region and the first plane;

the first electrode in contact with the second portions and the fourth silicon carbide region; and

the second electrode,

wherein an occupied area per unit area of the fourth silicon carbide region projected onto the first plane is larger than an occupied area per the unit area of the second silicon carbide region projected onto the first plane,

wherein a first diode region being one of the at least one diode region is provided between a first transistor region and a second transistor region, the first transistor region is one of the transistor regions, the second transistor region is one of the transistor regions provided in a first direction with respect to the first transistor region, and

wherein the first transistor region includes a third electrode provided on a side of the first plane of the silicon carbide layer and separated from the first electrode;

a first conductor having one end in contact with the first electrode and applying a voltage to the first electrode; and

a second conductor having one end in contact with the third electrode and applying a voltage to the third electrode,

wherein a distance between the third electrode and the first electrode is 100 μm or less.

5 . A semiconductor device comprising:

a semiconductor chip including a plurality of transistor regions and at least one diode region,

wherein the transistor regions include:

a silicon carbide layer having a first plane and a second plane facing the first plane, the silicon carbide layer including a first silicon carbide region of n-type having a plurality of first portions in contact with the first plane, a second silicon carbide region of p-type provided between the first silicon carbide region and the first plane, and a third silicon carbide region of n-type provided between the second silicon carbide region and the first plane;

a first electrode in contact with the first portions, the second silicon carbide region, and the third silicon carbide region;

a second electrode in contact with the second plane;

a gate electrode facing the second silicon carbide region; and

a gate insulating layer provided between the gate electrode and the second silicon carbide region,

wherein the at least one diode region includes:

the silicon carbide layer including the first silicon carbide region of n-type having a plurality of second portions in contact with the first plane and a fourth silicon carbide region of p-type provided between the first silicon carbide region and the first plane;

the first electrode in contact with the second portions and the fourth silicon carbide region; and

the second electrode,

wherein an occupied area per unit area of the fourth silicon carbide region projected onto the first plane is larger than an occupied area per the unit area of the second silicon carbide region projected onto the first plane,

wherein a first diode region being one of the at least one diode region is provided between a first transistor region and a second transistor region, the first transistor region is one of the transistor regions, the second transistor region is one of the transistor regions provided in a first direction with respect to the first transistor region, and

wherein the first transistor region includes a third electrode provided on a side of the first plane of the silicon carbide layer and separated from the first electrode;

a first conductor having one end in contact with the first electrode and applying a voltage to the first electrode; and

a second conductor having one end in contact with the third electrode and applying a voltage to the third electrode,

wherein an area of the third electrode is 10% or less of an area of the first electrode.

6 . The semiconductor device according to claim 1 , wherein each of the first conductor and the second conductor is a bonding wire.

7 . The semiconductor device according to claim 1 , wherein a contact area per the unit area between the first electrode and the fourth silicon carbide region is larger than a contact area per the unit area between the first electrode and the second silicon carbide region.

8 . The semiconductor device according to claim 1 , wherein a second distance between two of the second portions adjacent to each other with the fourth silicon carbide region interposed therebetween is equal to a first distance between two of the first portions adjacent to each other with the second silicon carbide region interposed therebetween.

9 . An inverter circuit comprising the semiconductor device according to claim 1 .

10 . A driving device comprising the semiconductor device according to claim 1 .

11 . A vehicle comprising the semiconductor device according to claim 1 .

12 . An elevator comprising the semiconductor device according to claim 1 .

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (21)