Lossless average input and output current sensing in a switched-mode power supply
Methods and apparatus for current sensing and error correction in a switched-mode power supply composed of a high-side transistor coupled to a low-side transistor are described. One example method generally includes capturing a current associated with the low-side transistor at a first time corresponding to the low-side transistor turning off; capturing a current associated with the high-side transistor at a second time corresponding to a first delay after the high-side transistor turns on; capturing the current associated with the high-side transistor at a third time corresponding to the high-side transistor turning off; and applying a first correction current to a current-summing node of the current-sensing circuit for a first interval based on the first delay, wherein the first correction current is based on the captured current associated with the low-side transistor at the first time and on the captured current associated with the high-side transistor at the second time.
1. A method of current sensing and correction for a switched-mode power supply comprising a high-side transistor and a low-side transistor coupled to the high-side transistor, the method comprising:
capturing, with a current-sensing circuit, a current associated with the low-side transistor at a first time corresponding to the low-side transistor turning off;
capturing a current associated with the high-side transistor at a second time corresponding to a first delay after the high-side transistor turns on;
capturing the current associated with the high-side transistor at a third time corresponding to the high-side transistor turning off; and
applying a first correction current to a current-summing node of the current-sensing circuit for a first interval based on the first delay, wherein the first correction current is based on the captured current associated with the low-side transistor at the first time and on the captured current associated with the high-side transistor at the second time.
2. The method of claim 1 , wherein the first delay is based on a blanking time and a settling time for a high-side current-sensing amplifier coupled to the high-side transistor, such that the high-side current-sensing amplifier corresponds to an inductor current for the switched-mode power supply by the second time.
3. The method of claim 1 , further comprising averaging the captured current associated with the low-side transistor at the first time and the captured current associated with the high-side transistor at the second time to obtain an averaged current, wherein the first correction current is the averaged current.
4. The method of claim 1 , wherein the first interval equals the first delay.
5. The method of claim 1 , further comprising determining an average input current for the switched-mode power supply based on the first correction current, the captured current associated with the high-side transistor at the second time, the captured current associated with the high-side transistor at the third time, and a duty cycle of the switched-mode power supply.
6. The method of claim 1 , further comprising:
capturing the current associated with the low-side transistor at a fourth time corresponding to a second delay after the low-side transistor turns on; and
applying a second correction current to the current-summing node for a second interval based on the second delay, wherein the second correction current is based on the captured current associated with the high-side transistor at the third time and on the captured current associated with the low-side transistor at the fourth time.
7. The method of claim 6 , wherein the second delay is based on a blanking time and a settling time for a low-side current-sensing amplifier coupled to the low-side transistor, such that the low-side current-sensing amplifier corresponds to an inductor current for the switched-mode power supply by the fourth time.
8. The method of claim 6 , further comprising averaging the captured current associated with the high-side transistor at the third time and the captured current associated with the low-side transistor at the fourth time to obtain an averaged current, wherein the second correction current is the averaged current.
9. The method of claim 6 , wherein the second interval equals the second delay.
10. The method of claim 6 , wherein:
the first time, the second time, the third time, and the fourth time occur during a first switching period of the switched-mode power supply;
the first interval occurs during a second switching period of the switched-mode power supply while the high-side transistor is turned on;
the second switching period is subsequent to the first switching period; and
the second interval occurs during the second switching period of the switched-mode power supply while the low-side transistor is turned on.
11. The method of claim 6 , further comprising:
capturing the current associated with the low-side transistor at a fifth time corresponding to the low-side transistor turning off, wherein a time difference between the fifth time and the first time is one switching period for the switched-mode power supply; and
determining an average output current for the switched-mode power supply based on the first correction current, the captured current associated with the high-side transistor at the second time, the captured current associated with the high-side transistor at the third time, the second correction current, the captured current associated with the low-side transistor at the fourth time, and the captured current associated with the low-side transistor at the fifth time.
12. A current-sensing circuit for a switched-mode power supply comprising a high-side transistor and a low-side transistor coupled to the high-side transistor, the current-sensing circuit comprising:
a high-side current-sensing amplifier having an input for coupling to the high-side transistor;
a low-side current-sensing amplifier having an input for coupling to the low-side transistor;
a first sample-and-hold circuit coupled to an output of the low-side current-sensing amplifier and configured to capture a current associated with the low-side transistor at a first time corresponding to the low-side transistor turning off;
a second sample-and-hold circuit coupled to an output of the high-side current-sensing amplifier and configured to capture a current associated with the high-side transistor at a second time corresponding to a first delay after the high-side transistor turns on;
a third sample-and-hold circuit coupled to the output of the high-side current-sensing amplifier and configured to capture the current associated with the high-side transistor at a third time corresponding to the high-side transistor turning off;
a first voltage-to-current converter having an input coupled to an output of the first sample-and-hold circuit and to an output of the second sample-and-hold circuit;
a first switch coupled between an output of the high-side current-sensing amplifier and a sensing node for the current-sensing circuit; and
a second switch coupled between an output of the first voltage-to-current converter and the sensing node.
13. The current-sensing circuit of claim 12 , further comprising:
a fourth sample-and-hold circuit coupled to the output of the low-side current-sensing amplifier and configured to capture the current associated with the low-side transistor at a fourth time corresponding to a second delay after the low-side transistor turns on;
a second voltage-to-current converter having an input coupled to an output of the third sample-and-hold circuit and to an output of the fourth sample-and-hold circuit; and
a third switch coupled between an output of the second voltage-to-current converter and the sensing node.
14. The current-sensing circuit of claim 13 , further comprising:
a fourth switch having a first terminal coupled to the output of the second sample-and-hold circuit and having a second terminal coupled to the output of the first sample-and-hold circuit and to the input of the first voltage-to-current converter; and
a fifth switch having a first terminal coupled to the output of the third sample-and-hold circuit and having a second terminal coupled to the output of the fourth sample-and-hold circuit and to the input of the second voltage-to-current converter.
15. The current-sensing circuit of claim 13 , further comprising
a third voltage-to-current converter having an input coupled to the output of the first sample-and-hold circuit and to the output of the second sample-and-hold circuit;
a fourth switch coupled between an output of the third voltage-to-current converter and an input-current-sensing node; and
a fifth switch coupled between the output of the high-side current-sensing amplifier and the input-current-sensing node.
16. The current-sensing circuit of claim 15 , further comprising a sixth switch coupled between the input-current-sensing node and a reference potential node.
17. The current-sensing circuit of claim 12 , further comprising a shunt resistor coupled between an output of the high-side current-sensing amplifier and a reference potential node, wherein the output of the high-side current-sensing amplifier is coupled to the output of the low-side current-sensing amplifier.
18. The current-sensing circuit of claim 17 , wherein the shunt resistor has a resistance and wherein the first voltage-to-current converter is configured to have a transconductance inversely proportional to the resistance of the shunt resistor.
19. The current-sensing circuit of claim 12 , further comprising:
a first shunt resistor coupled between an output of the high-side current-sensing amplifier and a reference potential node;
a second shunt resistor coupled between an output of the low-side current-sensing amplifier and the reference potential node; and
a third switch coupled between the output of the low-side current-sensing amplifier and the sensing node.
20. The current-sensing circuit of claim 12 , further comprising at least one of a low-pass filter or an error amplifier having an input coupled to the sensing node.