Reducing supply to ground current
An apparatus to prevent supply-to-ground current in a comparator is disclosed. The apparatus includes circuitry to determine if first and second output nodes of the comparator have respectively reached first and second logic levels, and circuitry responsive to a determination that the voltage at the first and second output nodes of the comparator has reached the first and second logic levels, to generate a signal. In addition, the apparatus includes circuitry to supply the signal to a transistor, the signal to turn off the transistor and prevent the flow of supply-to-ground current through the comparator.
1. An apparatus comprising:
an inverter having a clock input and an output;
a NOR gate having a first input, a second input, and an output, the first input adapted to be coupled to a first output of a comparator and the second input adapted to be coupled to a second output of the comparator;
a NAND gate having a first input, a second input, and an output, the first input is coupled to the output of the NOR gate and the second input is coupled to the output of the inverter; and
a transistor having a gate electrode, a source electrode, and a drain electrode, the gate electrode is coupled to the output of the NAND gate.
2. The apparatus of claim 1 , wherein the source electrode of the transistor is adapted to be coupled to a supply voltage source.
3. The apparatus of claim 1 , further comprising a second transistor having a source electrode and a third transistor having a source electrode, and wherein the drain electrode of the transistor is coupled to: (1) the source electrode of the second transistor; and (2) the source electrode of the third transistor.
4. The apparatus of claim 1 , further comprising a plurality of transistors coupled to the transistor.
5. The apparatus of claim 1 , further comprising a second transistor having a gate electrode, a source electrode, and a drain electrode, the gate electrode of the second transistor is coupled to the output of the NAND gate.
6. The apparatus of claim 1 , wherein the comparator includes a differential amplifier and a latch.
7. An method comprising:
receiving, by an inverter, a clock signal;
receiving, by a NOR gate, a first output of a comparator and a second output of the comparator;
receiving, by a NAND gate, an output from the NOR gate and an output from the inverter;
supplying, by the NAND gate, a signal to a transistor.
8. The method of claim 7 , wherein the transistor is coupled to a supply voltage source.
9. The method of claim 7 , wherein the comparator includes a differential amplifier and a latch.