Device programming system with multiple-device interface and method of operation thereof

1. A method of operation of a device programming system comprising:

detecting a device type of a first programmable device placed in communication with the device programming system;

retrieving a programming driver based on the device type;

configuring a field programmable gate array unit using the programming driver; and

configuring the first programmable device and a second programmable device simultaneously using a master image and the field programmable gate array unit.

2. The method as claimed in claim 1 further comprising:

creating a plurality of algorithm programming modules executing in independent parallel processing threads; and

wherein:

detecting the device type includes detecting the device type of the first programmable device in one of the independent parallel processing threads.

3. The method as claimed in claim 1 further comprising:

creating a plurality of algorithm programming modules executing in the independent parallel processing threads; and

wherein:

configuring the first programmable device includes configuring the first programmable device and the second programmable device in independent parallel processing threads.

4. The method as claimed in claim 1 wherein configuring the first programmable device includes configuring the first programmable device and the second programmable device from portions of the master image stored in a programmer memory unit.

5. The method as claimed in claim 1 wherein configuring the first programmable device includes configuring the second programmable device using a second programming driver.

6. A method of operation of a device programming system comprising:

partitioning a master image into slices;

detecting a first device type of a first programmable device placed in communication with the device programming system;

retrieving a programming driver based on the first device type;

configuring a field programmable gate array unit using the programming driver; and

configuring the first programmable device and a second programmable device simultaneously using the slices of the master image and the field programmable gate array unit.

7. The method as claimed in claim 6 wherein partitioning the master image includes partitioning the master image with the slices having a block size based on the first programmable device.

8. The method as claimed in claim 6 wherein detecting the first device type can include detecting a second device type of the second programmable device.

9. The method as claimed in claim 6 wherein the master image is stored in a system storage unit.

10. The method as claimed in claim 6 wherein configuring the first programmable device includes configuring the second programmable device based on a second device type.

11. A device programming system comprising:

a device programmer having a first programmable device mounted in a first destination socket; and

a field programmable gate array unit configured using a programming driver retrieved based on a device type of the first programmable device, and the device programmer configured to program a master image into the first programmable device and a second programmable device,

wherein the first programmable device and the second programmable device are configured using slices of the master image, and the second programmable device has a second device type,

wherein the first programmable device and the second programmable device are configured using slices of the master image.

12. The system as claimed in claim 11 further comprising:

a plurality of algorithm programming modules executing in independent parallel processing threads; and

wherein:

the first programmable device having the device type determined in one of the independent parallel processing threads.

13. The system as claimed in claim 11 further comprising:

a plurality of algorithm programming modules executing in independent parallel processing threads; and

wherein:

the first programmable device and the second programmable device are programmed in the independent parallel processing threads.

14. The system as claimed in claim 11 wherein the master image is partitioned into the slices having a block size based on the first programmable device.

15. The system as claimed in claim 11 further comprising a system storage unit for storing the master image.

16. The system as claimed in claim 11 wherein the second programmable device is configured based on a second device type.