Nonvolatile memory device and operation method thereof

1. An operation method of a nonvolatile memory device including a signal storage circuit, a debugging information generator, and a debugging information register, the method comprising:

receiving, by the signal storage circuit, control signals and a data signal from external of the nonvolatile memory device;

generating, by the debugging information generator, debugging information based on the control signals and the data signal;

receiving a debugging information request from external of the nonvolatile memory device; and

outputting, by the debugging information register, the debugging information in response to the debugging information request.

2. The method of claim 1 , wherein the debugging information request includes a debugging mode, and wherein the outputting of the debugging information comprises outputting information corresponding to the debugging mode.

3. The method of claim 1 , further comprising storing, by the signal storage circuit, the data signal as the debugging information when a rising edge of a write enable signal included in the control signals is detected.

4. The method of claim 1 , further comprising:

storing, by the signal storage circuit, a first value as the debugging information when a command latch enable signal included in the control signals is at a high level and a rising edge of a write enable signal included in the control signals is detected; and

storing, by the signal storage circuit, a second value as the debugging information when an address latch enable signal included in the control signals is at a high level and another rising edge of the write enable signal included in the control signals is detected.

5. The method of claim 4 , further comprising storing, by the signal storage circuit, a third value as the debugging information when a rising edge or a falling edge of a data strobe signal included in the control signals is detected.

6. The method of claim 1 , wherein the generating of the debugging information by the debugging information generator comprises:

determining a validity of a command and an address included in the data signal based on a preset value; and

generating a value corresponding to the determined validity as the debugging information.

7. The method of claim 1 , wherein the generating of the debugging information by the debugging information generator comprises:

determining a validity of a command included in the data signal and a validity of an address included in the data signal based on preset values; and

generating a number of valid commands and a number of valid addresses as the debugging information based on the determined validities.

8. The method of claim 1 , wherein the generating of the debugging information by the debugging information generator comprises:

determining a validity of a command included in the data signal based on a preset value; and

calculating a number of valid operations corresponding to the command as the debugging information based on the determined validity.

9. The method of claim 8 , wherein the number of valid operations is calculated for each type of an operation that the command indicates.

10. The method of claim 1 , further comprising storing, by the signal storage circuit, input signals received through different pins of the nonvolatile memory device when a rising edge or a falling edge of one of the control signals is detected, and

wherein the generating of the debugging information by the debugging information generator comprises:

determining a validity of a combination of the input signals based on a combination of preset signals; and

generating a value corresponding to the determined validity as the debugging information.

11. A nonvolatile memory device comprising:

a signal storage circuit configured to store control signals and a data signal received from external of the nonvolatile memory device;

a debugging information generator configured to generate debugging information based on the stored control signals and the stored data signal; and

a debugging information register configured to output the debugging information in response to a debugging information request from external of the nonvolatile memory device.

12. The nonvolatile memory device of claim 11 , wherein the debugging information request includes a debugging mode, and

wherein the debugging information register is configured to output information corresponding to the debugging mode as the debugging information.

13. The nonvolatile memory device of claim 11 , wherein the signal storage circuit is configured to store the data signal as the debugging information when a rising edge of a write enable signal included in the control signals is detected.

14. The nonvolatile memory device of claim 11 , wherein the signal storage circuit is configured to store a first value as the debugging information when a command latch enable signal included in the control signals is at a high level and a rising edge of a write enable signal included in the control signals is detected, and

wherein the signal storage circuit is configured to store a second value as the debugging information when an address latch enable signal included in the control signals is at a high level and another rising edge of the write enable signal included in the control signals is detected.

15. The nonvolatile memory device of claim 11 , wherein the debugging information generator is configured to determine a validity of a command and an address included in the data signal based on a preset value, and to generate a value corresponding to the determined validity as the debugging information.

16. The nonvolatile memory device of claim 11 , wherein the debugging information generator is configured to determine a validity of a command included in the data signal and a validity of an address included in the data signal based on preset values, and to calculate a number of valid commands and a number of valid addresses as the debugging information based on the determined validity.

17. The nonvolatile memory device of claim 11 , wherein the debugging information generator is configured to determine a validity of a command included in the data signal based on a preset value, and to calculate a number of valid operations corresponding to the command as the debugging information based on the determined validity.

18. The nonvolatile memory device of claim 11 , wherein the signal storage circuit is configured to store input signals received through different pins when a rising edge or a falling edge of one of the control signals is detected, and

wherein the debugging information generator is configured to determine a validity of a combination of the input signals based on a combination of preset signals, and to generate a value corresponding to the determined validity as the debugging information.

19. A nonvolatile memory package comprising:

an interface chip configured to receive control signals and a data signal through an external channel connected with a memory controller;

a first nonvolatile memory device configured to receive first control signals and a first data signal through a first internal channel connected with the interface chip; and

a second nonvolatile memory device configured to receive second control signals and a second data signal through a second internal channel connected with the interface chip,

wherein the interface chip comprises a debugging support circuit configured to output first and second debugging information in response to a debugging information request from the memory controller, and

wherein the debugging support circuit is configured to generate the first debugging information associated with the first nonvolatile memory device from the first control signals and the first data signal, and to generate the second debugging information associated with the second nonvolatile memory device from the second control signals and the second data signal.

20. The nonvolatile memory package of claim 19 , wherein the debugging support circuit is configured to output the first debugging information through the external channel when the debugging support circuit receives from the memory controller the debugging information request as comprising a first request for the first nonvolatile memory device, and

wherein the debugging support circuit is configured to output the second debugging information through the external channel when the debugging support circuit receives from the memory controller the debugging information request as comprising a second request for the second nonvolatile memory device.