Methods of memory address verification and memory devices employing the same
A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, and a controller configured to receive a data word to be stored at an address in the array and to store, at the address in the array, the data word and a location indicia corresponding to the address. The controller can be further configured to command the array to read the data word from the address, to receive response data from the array, and to verify that a location indicia of the response data corresponds to the address. If the location indicia of the response data does not correspond to the address, the controller can be further configured to indicate an error.
1. A method of operating a memory device including an array of memory cells, comprising:
commanding the array to perform a read operation at an address in the array;
receiving response data from the array, the response data corresponding to the read operation and comprising a data word and a location indicia; and
verifying that the location indicia of the response data corresponds to the address.
2. The method of claim 1 , further comprising:
indicating an error if the location indicia of the response data does not correspond to the address.
3. The method of claim 1 , further comprising:
outputting the data word if the location indicia of the response data corresponds to the address.
4. The method of claim 1 , wherein the location indicia is a hash of the address.
5. The method of claim 1 , wherein the address corresponds to a row of the array, and wherein the location indicia corresponds to the row.
6. The method of claim 1 , wherein the location indicia is the address.
7. The method of claim 1 , wherein the location indicia is prepended or appended to the data word.
8. The method of claim 1 , wherein the data word comprises a plurality of bits.
9. An apparatus configured to:
command an array of memory cells to perform a read operation at an address in the array;
receive response data from the array, the response data corresponding to the read operation and comprising a data word and a location indicia; and
verify that the location indicia of the response data corresponds to the address.
10. The apparatus of claim 9 , further configured to:
indicate an error if the location indicia of the response data does not correspond to the address.
11. The apparatus of claim 9 , further configured to:
output the data word if the location indicia of the response data corresponds to the address.
12. The apparatus of claim 9 , wherein the location indicia is a hash of the address.
13. The apparatus of claim 9 , wherein the address corresponds to a row of the array, and wherein the location indicia corresponds to the row.
14. The apparatus of claim 9 , wherein the location indicia is the address.
15. The apparatus of claim 9 , wherein the location indicia is prepended or appended to the data word.
16. The apparatus of claim 9 , wherein the data word comprises a plurality of bits.
17. A memory device, comprising:
an array of memory cells; and
a memory controller configured to:
command the array to perform a read operation at an address in the array;
receive response data from the array, the response data corresponding to the read operation and comprising a data word and a location indicia; and
verify that the location indicia of the response data corresponds to the address.
18. The memory device of claim 17 , wherein the memory controller is further configured to:
indicate an error if the location indicia of the response data does not correspond to the address.
19. The memory device of claim 17 , wherein the memory controller is further configured to:
output the data word if the location indicia of the response data corresponds to the address.
20. The memory device of claim 17 , wherein the location indicia is prepended or appended to the data word.