IP Library › Granted Patent US 10,762,392
Granted Patent B2
US 10,762,392 · App. 16/234,956 · Granted Sep 1, 2020

Tiling format for convolutional neural networks

Inventors: Song Zhang (Shanghai, CN); Jiantan Liu (Shanghai, CN); Hua Zhang (Shanghai, CN); Min Yu (Shanghai, CN)
Assignee: Advanced Micro Devices, Inc.
G06K9/6262G06N3/04G06N3/08
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Quick Facts
Patent No.
US 10,762,392
App. No.
16/234,956
Granted
Sep 1, 2020
Kind
B2
Abstract

Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.

Claims (53)

1. A system comprising:

a memory storing a first buffer and a second buffer in a linear format, wherein the first buffer stores convolutional filter data and the second buffer stores image data;

a cache;

a processor configured to:

convert the convolutional filter data in the first buffer from the linear format to a tiling format and store in a third buffer; and

convert the image data in the second buffer from the linear format to the tiling format and store in a fourth buffer; and

a plurality of compute units, wherein the plurality of compute units are configured to:

load data elements of the third buffer and the fourth buffer from the memory to the cache; and

perform a convolutional filter operation on the data elements of the third buffer and the fourth buffer to generate a result in the tiling format;

wherein the system is configured to generate a classification of a first dataset based on the result from the convolutional filter operation.

2. The system as recited in claim 1 , wherein the cache comprises a plurality of channels, wherein the plurality of compute units are configured to load convolutional filter data elements from the third buffer on the plurality of channels in parallel in a single clock cycle.

3. The system as recited in claim 1 , wherein the cache comprises a plurality of channels, wherein the plurality of compute units are configured to load image data elements from the fourth buffer on the plurality of channels in parallel in a single clock cycle.

4. The system as recited in claim 1 , wherein converting the first buffer from the linear format to the third buffer in the tiling format comprises:

reading values from sequential locations of the first buffer in the memory; and

stepping through the third buffer with a stride equal to a sum of a first number of input channels and a second number of convolutional filters while writing the values to the third buffer.

5. The system as recited in claim 1 , wherein converting the second buffer from the linear format to the fourth buffer in the tiling format comprises:

reading values from sequential locations of the second buffer in the memory; and

stepping through the fourth buffer with a stride equal to a number of pixel channels while writing the values to the fourth buffer.

6. The system as recited in claim 1 , wherein the convolutional filter data comprises a plurality of convolutional filters, wherein each convolutional filter of the plurality of convolutional filters has three rows and three columns.

7. The system as recited in claim 1 , wherein the classification of the first dataset is generated during execution of a machine learning engine application.

8. A method comprising:

storing, by a memory, a first buffer and a second buffer in a linear format, wherein the first buffer stores convolutional filter data and the second buffer stores image data;

converting, by a processor, the convolutional filter data in the first buffer from the linear format to a tiling format and store in a third buffer;

converting, by a processor, the image data in the second buffer from the linear format to the tiling format and store in a fourth buffer;

loading, by a plurality of compute units, data elements of the third buffer and the fourth buffer from the memory to a cache;

performing, by a plurality of compute units, a convolutional filter operation on the data elements of the third buffer and the fourth buffer to generate a result in the tiling format;

and

generating a classification of a first dataset based on the result from the convolutional filter operation.

9. The method as recited in claim 8 , wherein the cache comprises a plurality of channels, and wherein the method further comprising loading, by the plurality of compute units, convolutional filter data from the third buffer on the plurality of channels in parallel in a single clock cycle.

10. The method as recited in claim 8 , wherein the cache comprises a plurality of channels, and wherein the method further comprising loading, by the plurality of compute units, image data from the fourth buffer on the plurality of channels in parallel in a single clock cycle.

11. The method as recited in claim 8 , wherein converting the first buffer from the linear format to the third buffer in the tiling format comprises:

reading values from sequential locations of the first buffer in the memory; and

stepping through the third buffer with a stride equal to a sum of a first number of input channels and a second number of convolutional filters while writing the values to the third buffer.

12. The method as recited in claim 8 , wherein converting the second buffer from the linear format to the fourth buffer in the tiling format comprises:

reading values from sequential locations of the second buffer in the memory; and

stepping through the fourth buffer with a stride equal to a number of pixel channels while writing the values to the fourth buffer.

13. The method as recited in claim 8 , wherein the convolutional filter data comprises a plurality of convolutional filters, wherein each convolutional filter of the plurality of convolutional filters has three rows and three columns.

14. The method as recited in claim 8 , further comprising generating the classification of the first dataset during execution of a machine learning engine application.

15. An apparatus comprising:

a memory storing a first buffer and a second buffer in a linear format, wherein the first buffer stores convolutional filter data and the second buffer stores image data; and

a processor configured to:

convert the convolutional filter data in the first buffer from the linear format to a tiling format and store in a third buffer; and

convert the image data in the second buffer from the linear format to the tiling format and store in a fourth buffer; and

generate a classification of a first dataset based on a result from a convolutional filter operation performed on data elements stored in the tiling format in the third buffer and the fourth buffer.

16. The apparatus as recited in claim 15 , further comprising a cache, wherein the cache comprises a plurality of channels, and wherein the apparatus is further configured to load convolutional filter data from the third buffer on the plurality of channels in parallel in a single clock cycle.

17. The apparatus as recited in claim 15 , further comprising a cache, wherein the cache comprises a plurality of channels, and wherein the apparatus is further configured to load image data from the fourth buffer on the plurality of channels in parallel in a single clock cycle.

18. The apparatus as recited in claim 15 , wherein converting the first buffer from the linear format to the third buffer in the tiling format comprises:

reading values from sequential locations of the first buffer in the memory; and

stepping through the third buffer with a stride equal to a sum of a first number of input channels and a second number of convolutional filters while writing the values to the third buffer.

19. The apparatus as recited in claim 15 , wherein converting the second buffer from the linear format to the fourth buffer in the tiling format comprises:

reading values from sequential locations of the second buffer in the memory; and

stepping through the fourth buffer with a stride equal to a number of pixel channels while writing the values to the fourth buffer.

20. The apparatus as recited in claim 15 , wherein the classification of the first dataset is generated during execution of a machine learning engine application.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2018
From: ZHANG, SONG; LIU, JIANTAN; ZHANG, HUA; YU, MIN
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 047866/0906 →
Priority Claims (1)
CN 2018 1 1563959 · Dec 20, 2018 · national
Continuity (1)
Related Publication 20200202180A1 · Jun 25, 2020
Cited By (3)
US 12,265,908 US 12,670,373 US 12,738,018