Memory structure with multi-cell poly pitch
Various implementations described herein refer to an integrated circuit having a memory structure with a two-bitcell layout and a four cell poly pitch. The two-bitcell layout includes a first bitcell and a second bitcell with structural contours that are joined together in a coupling arrangement. The first bitcell and the second bitcell have multiple transistors that are arranged to store data during write operations and allow access of data during read operations.
1. An integrated circuit, comprising:
a memory structure having a two-bitcell layout with a four cell poly pitch,
wherein the two-bitcell layout includes a first bitcell and a second bitcell having structural contours that are joined together in a coupling arrangement, and
wherein the first bitcell and the second bitcell have multiple transistors arranged to store data during write operations and allow access of data during read operations.
2. The integrated circuit of claim 1 , wherein the first bitcell and the second bitcell have non-linear structural contours that are joined together in a reciprocal arrangement.
3. The integrated circuit of claim 2 , wherein the non-linear structural contours refer to L-shaped structural contours that are joined together in the reciprocal arrangement.
4. The integrated circuit of claim 1 , wherein the memory structure comprises a multi-port memory structure.
5. The integrated circuit of claim 4 , wherein the multi-port memory structure refers to a two-port memory structure with a dedicated write port and a dedicated read port.
6. The integrated circuit of claim 1 , wherein the first bitcell and the second bitcell are eight transistor (8T) bitcells.
7. The integrated circuit of claim 1 , further comprising:
a write wordline coupled to the first bitcell and the second bitcell; and
a read wordline coupled to the first bitcell and the second bitcell,
wherein the first bitcell and the second bitcell share the write wordline and the read wordline.
8. The integrated circuit of claim 7 , wherein the two-bitcell layout with the four cell poly pitch reduces vertical wordline resistance and capacitance of the write wordline and the read wordline.
9. The integrated circuit of claim 1 , further comprising:
a first pair of write bitlines coupled to the first bitcell; and
a second pair of write bitlines coupled to the second bitcell.
10. The integrated circuit of claim 1 , further comprising:
a first read bitline coupled to the first bitcell; and
a second read bitline coupled to the second bitcell.
11. An integrated circuit, comprising:
a memory structure having a two-bitcell layout in a coupling arrangement,
wherein the two-bitcell layout includes a first bitcell and a second bitcell having non-linear structural contours that are joined together in the coupling arrangement, and
wherein the first bitcell and the second bitcell have multiple transistors arranged to store data during write operations and allow access of data during read operations, wherein the non-linear structural contours refer to L-shaped structural contours that are joined together in a reciprocal arrangement.
12. The integrated circuit of claim 11 , wherein the two-bitcell layout has a four cell poly pitch.
13. An integrated circuit, comprising:
a memory structure having a two-bitcell layout in a coupling arrangement,
wherein the two-bitcell layout includes a first bitcell and a second bitcell having structural contours that are joined together in the coupling arrangement, and wherein the first bitcell and the second bitcell have multiple transistors arranged to store data during write operations and allow access of data during read operations, wherein the memory structure comprises a multi-port memory structure.
14. The integrated circuit of claim 13 , wherein the multi-port memory structure refers to a two-port memory structure with a dedicated write port and a dedicated read port.
15. An integrated circuit, comprising:
a memory structure having a two-bitcell layout in a coupling arrangement,
wherein the two-bitcell layout includes a first bitcell and a second bitcell having structural contours that are joined together in the coupling arrangement, and wherein the first bitcell and the second bitcell have multiple transistors arranged to store data during write operations and allow access of data during read operations, wherein the first bitcell and the second bitcell are eight transistor (8T) bitcells.
16. A method, comprising:
fabricating a memory structure having a two-bitcell layout with a four cell poly pitch;
fabricating the two-bitcell layout with a first bitcell and a second bitcell having structural contours that are joined together in a coupling arrangement; and
fabricating the first bitcell and the second bitcell with multiple transistors arranged to store data during write operations and allow access of data during read operations.
17. The method of claim 16 , further comprising:
fabricating the first bitcell and the second bitcell with non-linear structural contours that are joined together in a reciprocal arrangement.
18. The method of claim 17 , wherein the non-linear structural contours are L-shaped structural contours that are joined together in the reciprocal arrangement.
19. The method of claim 16 , wherein the first bitcell and the second bitcell are eight transistor (8T) bitcells.