Manufacture of power devices having inversion channel
An embodiment relates to a device comprising a unit cell on a SiC substrate, the unit cell comprising a first well region, a source region, a plug region, and a well trench, wherein the well trench has a depth that is less than that of the first well region. Additional embodiments relate to the device having a second well region, wherein the second well region has a depth that is equal to or deeper than the first well region and the second well region is located under and around the source region.
1. A device comprising a unit cell on a SiC substrate, the unit cell comprising:
a first well region,
a source region,
a plug region,
a well trench, and
a semiconductor channel comprising a first portion and a second portion;
wherein the first portion is located on a horizontal crystal plane of the SiC substrate and the second is located on a vertical crystal plane of the SiC substrate, and wherein the well trench has a depth that is less than that of the first well region,
wherein the source region located is within the first well region; and wherein the horizontal crystal plane comprises a 0001 crystal plane of the SiC substrate and the vertical crystal plane comprises a 11-20 or 10-10 crystal plane of the SiC substrate.
2. The device of claim 1 , wherein at least a portion of the plug region is located at a center of the unit cell.
3. The device of claim 1 , wherein the plug region is located between a source interconnect metallization region and the SiC substrate.
4. The device of claim 1 , wherein the plug region is located between least two well regions.
5. The device of claim 1 , wherein the plug region is located between at least two source regions.
6. The device of claim 1 , wherein the plug region is partially within the source region and extends beyond the source region.
7. The device of claim 1 , wherein at least a portion of the first well region is located between the source region and the SiC substrate.
8. The device of claim 1 , further comprising a drift layer.
9. The device of claim 8 , wherein the drift layer is located on the SiC substrate.
10. The device of claim 9 , wherein the unit cell is located within the drift layer.
11. The device of claim 1 , further comprising a second well region.
12. The device of claim 11 , wherein the second well region has a depth that is equal to or deeper than the first well region.
13. The device of claim 11 , wherein the second well region is located under and around the source region.
14. The device of claim 11 , wherein a lateral extent of the second well region is larger than the first well region.
15. The device of claim 11 , wherein the second well region is located between the source region and the SiC substrate.
16. The device of claim 1 , wherein the device comprises a n-type MOSFET or p-type MOSFET.
17. The device of claim 1 , wherein the device comprises a n-type DMOSFET or p-type DMOSFET.
18. The device of claim 1 , further comprising a drain region and a gate region.
19. The device of claim 1 , further comprising an interlayer dielectric.