Semiconductor switching device
A device having reduced Rds(on) is described. The device comprises a unit cell. The unit cell comprises: a first region, a second region, a third region, and a fourth region. The fourth region is residing on the first region, the second region, and the third region. The second region connects the first region and the third region. The first region, the second region and the third region are of same conductivity type (e.g., second conductivity type). In an embodiment, the fourth region comprises a fifth region and a sixth region. The fourth region, the fifth region, and the sixth region are of same conductivity type (e.g., first conductivity type). The fourth region is on the first region. The fifth region is on the second region. The sixth region is on the third region. In an embodiment, the device achieves reduced Rds(on) by relaxing the JFET constraint.
1. A device comprising:
a semiconductor unit cell, wherein the semiconductor unit cell comprises one or more semiconductor regions that are spatially arranged as:
a first region that comprises a first contact region,
a second region,
a third region,
a Metal-Insulator-Semiconductor (MIS) channel region;
a fourth region residing on the first region, and the third region, the fourth region that comprises
a fifth region, and
a sixth region,
wherein the one or more semiconductor regions comprises silicon carbide;
wherein the fourth region, the fifth region, and the sixth region are of same conductivity type;
wherein the fifth region and the sixth region are shallower than the fourth region;
wherein the second region connects the first region and the third region;
wherein the first region, the second region and the third region are of same conductivity type;
wherein the MIS channel region is located on at least one of the first region, the second region, and the third region; and
wherein the first contact region is formed on the first region.
2. The device of claim 1 , wherein the second region connects the first region and the third region with a periodicity at a fixed interval space.
3. The device of claim 1 , further comprising:
a seventh region that is surrounded by the first region, the second region and the third region,
wherein the seventh region and the fourth region are of same conductivity type.
4. The device of claim 3 , wherein the fourth region and the seventh region are of a first conductivity type.
5. The device of claim 1 , wherein the first region, the second region, and the third region are of a second conductivity type.
6. The device of claim 1 , wherein the fourth region, the fifth region, and the sixth region are of a first conductivity type.
7. The device of claim 1 , wherein the fourth region is on the first region.
8. The device of claim 1 , wherein the fifth region is on the second region.
9. The device of claim 1 , wherein the sixth region is on the third region.
10. The device of claim 1 , wherein the device further comprising:
an eighth region, wherein the eighth region is of a second conductivity type.
11. The device of claim 1 , further comprising a second contact region, wherein the second contact region is formed on the sixth region.
12. A device comprising:
a semiconductor unit cell, wherein the semiconductor unit cell comprises one or more semiconductor regions that are spatially arranged as:
a first region that comprises a first contact region,
a second region,
a third region,
a fourth region residing on the first region, and the third region; and
a seventh region that is surrounded by the first region, the second region and the third region,
wherein the second region connects the first region, and the third region;
wherein the first region, the second region, and the third region are of same conductivity type; and
wherein the first contact region is formed on the first region;
wherein the seventh region and the fourth region are of same conductivity type; and
wherein the seventh region comprises a plurality of depletion paths that extends inwards from a plurality of directions from the first region, the second region, and the third region towards a center of the seventh region.
13. The device of claim 12 , wherein the seventh region comprises a first dimension and a second dimension, wherein a ratio of the first dimension to the second dimension is in a range from 0.3 to 2.0.
14. The device of claim 12 , further comprising
a gate insulator region;
wherein the second region is not in contact with the gate insulator region.
15. The device of claim 14 , wherein the second region comprises laterally straggled ions from the first region and the third region.
16. The device of claim 14 , further comprising an eighth region located below a trench region.
17. The device of claim 12 , wherein the fourth region is also residing on the second region.