Buck-boost DC-DC converter
Disclosed examples include inverting buck-boost DC-DC converter circuits with a switching circuit to alternate between first and second buck mode phases for buck operation in a first mode, including connecting an inductor and a capacitor in series between an input node and a reference node to charge the inductor and the capacitor in the first buck mode phase, and connecting the inductor and the capacitor in parallel between an output node and the reference node to discharge the inductor and the capacitor to the output node. For boost operation in a second mode, the switching circuit alternates between connecting the inductor and the capacitor in series between the input node and the reference node to discharge the inductor and charge the capacitor in a first boost mode phase, and connecting the inductor between the input node and the reference node to charge the inductor and connecting the capacitor between the first output node and the reference node to discharge the capacitor to deliver power to the output node in a second boost mode phase.
1. A voltage converter comprising:
an input terminal;
an output terminal;
a first switching node adapted to be coupled to an inductor;
a second switching node adapted to be coupled to a capacitor;
an intermediate node adapted to be coupled between the inductor and the capacitor;
a first transistor coupled between the intermediate node and a ground reference node;
a second transistor coupled between the ground reference node and the second switching node;
a third transistor coupled between the second switching node and the output terminal; and
a controller configured to:
turn on the second transistor and turn off the first and third transistors during a first phase;
turn off the second transistor and turn on first and third transistors during a second phase; and
switch between the first and second phases based on a sense signal coupled to and indicative of a current conducted by the inductor.
2. The voltage converter of claim 1 , in which the input terminal is coupled to the first switching node.
3. The voltage converter of claim 2 , including:
a second output terminal; and
a fourth switch coupled between the intermediate node and the second output terminal.
4. The voltage converter of claim 1 , including:
a fourth transistor coupled between the input terminal and the first switching node; and
a fifth transistor coupled between the first switching node and the output terminal.
5. The voltage converter of claim 4 , in which: the first, second, and third transistors each has a first transistor size based on an absolute output voltage rating associated with the output terminal; the fourth transistor has a second transistor size based on an input voltage rating associated with the input terminal; and the fifth transistor has a third transistor size based on a sum of the input voltage rating and the absolute output voltage rating.
6. The voltage converter of claim 4 , including:
a controller operative in a boost mode and configured to:
turn on the fourth and second transistors and turn off the first, third, and fifth transistors during a first phase;
turn on the fourth, first, and third transistors and turn off second and fifth transistors during a second phase; and
switch between the first and second phases based on a sense signal coupled to and indicative of a current conducted by the inductor.
7. The voltage converter of claim 4 , including:
a controller operative in a buck mode and configured to:
turn on the fourth and second transistors and turn off the first, third, and fifth transistors during a first phase;
turn off the fourth and second transistors and turn on first, third, and fifth transistors during a second phase; and
switch between the first and second phases based on a sense signal coupled to and indicative of a current conducted by the inductor.
8. The voltage converter of claim 4 , including:
a controller operative in a buck-boost mode and configured to:
turn on the fourth, first, and third transistors and turn off second and fifth transistor during a first phase;
turn on the fourth and second transistors and turn off the first, third, and fifth transistors during a second phase;
turn on first, third, and fifth transistors and turn off the fourth and second transistors during a third phase; and
switch between the first, second, and third phases based on a sense signal coupled to and indicative of a current conducted by the inductor.
9. The voltage converter of claim 1 , including:
the inductor coupled between the first switching node and the intermediate node; and
the capacitor coupled between the intermediate node and the second switching node.
10. The voltage converter of claim 1 , including:
an integrated circuit having the first and second switching nodes, the intermediate node, and the first, second, and third transistors;
the inductor coupled between the first switching node and the intermediate node; and
the capacitor coupled between the intermediate node and the second switching node.
11. An integrated circuit comprising: an input terminal; an output terminal; a first switching node adapted to be coupled to an inductor; a second switching node adapted to be coupled to a capacitor; an intermediate node adapted to be coupled between the inductor and the capacitor; a first transistor coupled between the intermediate node and a ground reference node; a second transistor coupled between the ground reference node and the second switching node; a third transistor coupled between the second switching node and the output terminal a fourth transistor coupled between the input terminal and the first switching node; a fifth transistor coupled between the first switching node and the output terminal; and the first, second, and third transistors each has a first transistor size based on an absolute output voltage rating associated with the output terminal; the fourth transistor has a second transistor size based on an input voltage rating associated with the input terminal; and the fifth transistor has a third transistor size based on a sum of the input voltage rating and the absolute output voltage rating.
12. The integrated circuit of claim 11 , including:
a controller operative in a boost mode and configured to:
turn on the fourth and second transistors and turn off the first, third, and fifth transistors during a first phase;
turn on the fourth, first, and third transistors and turn off second and fifth transistors during a second phase; and
switch between the first and second phases based on a sense signal indicative of a current conducted by the inductor.
13. The integrated circuit of claim 11 , including:
a controller operative in a buck mode and configured to:
turn on the fourth and second transistors and turn off the first, third, and fifth transistors during a first phase;
turn off the fourth and second transistors and turn on first, third, and fifth transistors during a second phase; and
switch between the first and second phases based on a sense signal indicative of a current conducted by the inductor.
14. The integrated circuit of claim 11 , including:
a controller operative in a buck-boost mode and configured to:
turn on the fourth, first, and third transistors and turn off second and fifth transistor during a first phase;
turn on the fourth and second transistors and turn off the first, third, and fifth transistors during a second phase;
turn on first, third, and fifth transistors and turn off the fourth and second transistors during a third phase; and
switch between the first, second, and third phases based on a sense signal indicative of a current conducted by the inductor.
15. The integrated circuit of claim 11 , including:
the inductor coupled between the first switching node and the intermediate node; and
the capacitor coupled between the intermediate node and the second switching node.
16. A voltage converter comprising: an input terminal; an output terminal; an inductor; a capacitor coupled in series with the inductor at an intermediate node; a first transistor coupled between the intermediate node and a ground reference node; a second transistor coupled between the ground reference node and the capacitor; a third transistor coupled between the capacitor and the output terminal; a fourth transistor coupled between the input terminal and the inductor; a fifth transistor coupled between the inductor and the output terminal; the first, second, and third transistors each has a first transistor size based on an absolute output voltage rating associated with the output terminal; the fourth transistor has a second transistor size based on an input voltage rating associated with the input terminal; and the fifth transistor has a third transistor size based on a sum of the input voltage rating and the absolute output voltage rating.