Semiconductor integrated circuit

1. A semiconductor integrated circuit comprising:

a first input terminal that receives a control signal for controlling switching between an output mode and a non-output mode;

a second input terminal that receives an input data signal;

a power supply terminal that receives a power supply voltage;

an external terminal capable of receiving an external voltage higher than the power supply voltage in the non-output mode; and

a first PMOS transistor and a second PMOS transistor connected in series between the power supply terminal and the external terminal, wherein

a gate of the first PMOS transistor is driven:

by a signal corresponding to the input data signal in the output mode; and by the power supply voltage in the non-output mode, and

a gate of the second PMOS transistor is driven:

by a ground voltage in the output mode; and

in the non-output mode, where a critical voltage is lower than a sum of the power supply voltage and a threshold voltage of a MOS transistor, by the power supply voltage, if the external voltage received at the external terminal is lower than the critical voltage; and by the external voltage received at the external terminal, if the external voltage received at the external terminal is higher than or equal to the critical voltage, and

the critical voltage is higher than the power supply voltage.

2. The semiconductor integrated circuit of claim 1 , further comprising:

a third PMOS transistor connected between the gate of the second PMOS transistor and the external terminal; and

a bias voltage generating circuit including an output connected to a gate of the third PMOS transistor, wherein

the bias voltage generating circuit outputs:

the power supply voltage in the output mode; and

a voltage lower than the power supply voltage, if the external voltage received at the external terminal is at a high logic level in the non-output mode.

3. The semiconductor integrated circuit according to claim 2 , wherein

the bias voltage generating circuit outputs a voltage lower than the power supply voltage and higher than a difference obtained through subtraction of the threshold voltage of a MOS transistor from the power supply voltage, if the external voltage received at the external terminal is at the high logic level in the non-output mode.

4. The semiconductor integrated circuit according to claim 2 , wherein

the bias voltage generating circuit outputs a voltage lower than the power supply voltage, if the external voltage received at the external terminal is at a low logic level in the non-output mode.

5. The semiconductor integrated circuit according to claim 2 , wherein

the bias voltage generating circuit outputs the power supply voltage, if the external voltage received at the external terminal is at a low logic level in the non-output mode.

6. The semiconductor integrated circuit according to claim 2 , wherein

the bias voltage generating circuit includes a voltage divider circuit including a resistive element or a diode-connected MOS transistor.

7. The semiconductor integrated circuit according to claim 2 , wherein

the bias voltage generating circuit is configured to reduce current consumption of the bias voltage generating circuit, while the external voltage received at the external terminal maintains the high logic level in the non-output mode.

8. A semiconductor integrated circuit comprising:

a first input terminal that receives a control signal for controlling switching between an output mode and a non-output mode;

a second input terminal that receives an input data signal;

a power supply terminal that receives a power supply voltage;

an external terminal capable of receiving an external voltage higher than the power supply voltage in the non-output mode;

an output PMOS transistor connected between the power supply terminal and the external terminal,

an auxiliary PMOS transistor connected between the gate of the output PMOS transistor and the external terminal; and

a bias voltage generating circuit including an output connected to a gate of the auxiliary PMOS transistor, wherein

a gate of the output PMOS transistor is driven:

by a signal corresponding to the input data signal in the output mode; and in the non-output mode, where a critical voltage is lower than a sum of the power supply voltage and a threshold voltage of a MOS transistor, by the power supply voltage, if the external voltage received at the external terminal is lower than the critical voltage; and by the external voltage received at the external terminal, if the external voltage received at the external terminal is higher than or equal to the critical voltage,

the bias voltage generating circuit outputs:

the power supply voltage in the output mode; and

a voltage lower than the power supply voltage, if the external voltage received at the external terminal is at a high logic level in the non-output mode; and

a voltage lower than the power supply voltage, if the external voltage received at the external terminal is at a low logic level in the non-output mode.

9. The semiconductor integrated circuit according to claim 8 , wherein

the critical voltage is higher than the power supply voltage.

10. The semiconductor integrated circuit according to claim 8 , wherein

the bias voltage generating circuit outputs a voltage lower than the power supply voltage and higher than a difference obtained through subtraction of the threshold voltage of a MOS transistor from the power supply voltage, if the external voltage received at the external terminal is at the high logic level in the non-output mode.

11. The semiconductor integrated circuit according to claim 8 , wherein

the bias voltage generating circuit includes a voltage divider circuit including a resistive element or a diode-connected MOS transistor.

12. The semiconductor integrated circuit according to claim 8 , wherein

the bias voltage generating circuit is configured to reduce current consumption of the bias voltage generating circuit, while the external voltage received at the external terminal maintains the high logic level in the non-output mode.

13. A semiconductor integrated circuit comprising:

a power supply terminal;

an external terminal;

an output PMOS transistor connected between the power supply terminal and the external terminal;

an auxiliary PMOS transistor connected between the gate of the output PMOS transistor and the external terminal; and

a bias voltage generating circuit connected to a gate of the auxiliary PMOS transistor, wherein

the bias voltage generating circuit supplies a voltage lower than a power supply voltage to the gate of the auxiliary PMOS transistor, if it is necessary to maintain an OFF state of the output PMOS transistor by supplying an external voltage received at the external terminal to the gate of the output PMOS transistor, and

the bias voltage generating circuit is configured to reduce current consumption of the bias voltage generating circuit, while the external voltage received at the external terminal maintains a high logic level.

14. The semiconductor integrated circuit according to claim 13 , wherein

the voltage supplied from the bias voltage generating circuit to the gate of the auxiliary PMOS transistor is higher than a difference obtained through subtraction of a threshold voltage of a MOS transistor from the power supply voltage.

15. The semiconductor integrated circuit according to claim 13 , wherein

the bias voltage generating circuit is a voltage divider circuit including resistive elements or diode-connected MOS transistors.