Solid-state image pickup device and method for driving the same in solid-state imaging pickup device and method for driving the same in a number of modes
A system and method for driving a solid-state image pickup device including a pixel array unit including unit pixels. Each unit pixel includes a photoelectric converter, column signal lines and a number of analog-digital converting units. The unit pixels are selectively controlled in units of rows. Analog signals output from the unit pixels in a row selected by the selective control though the column signal lines are converted to digital signals via the analog-digital converting units. The digital signals are added among a number of unit pixels via the analog-digital converting units. The added digital signals from the analog-digital converting units are read. Each unit pixel in the pixel array unit is selectively controlled in units of arbitrary rows, the analog-distal converting units being operable to performing the converting in a (a) normal-frame-rate mode and a (b) high-frame-rate mode in response to control signals.
1. An imaging device, comprising:
a first pixel that outputs a first pixel signal;
a second pixel that outputs a second pixel signal;
a third pixel that outputs a third pixel signal;
a fourth pixel that outputs a fourth pixel signal;
a first signal line coupled to the first pixel;
a second signal line coupled to the second pixel;
a third signal line coupled to the third pixel;
a fourth signal line coupled to the fourth pixel;
first analog to digital conversion circuitry, a first input of the first analog to digital conversion circuitry being coupled to the first signal line;
second analog to digital conversion circuitry, a second input of the second analog to digital conversion circuitry being coupled to a first switch circuitry;
third analog to digital conversion circuitry, a third input of the third analog to digital conversion circuitry being coupled to a second switch circuitry;
fourth analog to digital conversion circuitry, a fourth input of the fourth analog to digital conversion circuitry being coupled to the fourth signal line;
a first output line coupled to a first output of the first analog to digital conversion circuitry and a third output of the third analog to digital conversion circuitry;
a second output line coupled to a second output of the second analog to digital conversion circuitry and a fourth output of the fourth analog to digital conversion circuitry;
wherein the first switch circuitry is configured to couple the second signal line to the second analog to digital conversion circuitry and couple the third signal line to the second analog to digital conversion circuitry selectively,
wherein the second switch circuitry is configured to couple the third signal line to the third analog to digital conversion circuitry and couple the second signal line to the third analog to digital conversion circuitry selectively,
wherein the first switch circuitry and second switch circuitry form an integrated switching pair, the integrated switching pair is provided between the second and third pixels and the second and third analog to digital conversion circuitries,
wherein when the integrated switching pair operates in a first mode, the first, second, third and fourth pixel signals are converted to digital signals by the first, second, third and fourth analog to digital conversion circuitries, respectively,
wherein when the integrated switching pair operates in a second mode, the first and third pixel signals are converted to digital signals by the first and second analog to digital conversion circuitries, respectively, and the second and fourth pixel signals are converted to digital signals by the third and fourth analog to digital conversion circuitries, and
wherein the first analog to digital conversion circuitry comprises a first comparator, the second analog to digital conversion circuitry comprises a second comparator, the third analog to digital conversion circuitry comprises a third comparator and the fourth analog to digital conversion circuitry comprises a fourth comparator.
2. The imaging device according to claim 1 , wherein the first analog to digital conversion circuitry is not coupled to the second output line and the second analog to digital conversion circuitry is not coupled to the first output line.
3. The imaging device according to claim 1 , wherein the first output line and the second output line are coupled to signal processing circuitry.
4. The imaging device according to claim 1 , wherein the first output line and the second output line are coupled to digital adder circuitry.
5. The imaging device according to claim 1 , further comprising reference signal generation circuitry coupled to the first analog to digital conversion circuitry and the second analog to digital conversion circuitry.
6. The imaging device according to claim 1 , wherein the first analog to digital conversion circuitry is configured to output a first digital signal to the first output line and the fourth analog to digital conversion circuitry is configured to output a forth digital signal to the second output line.
7. The imaging device according to claim 6 , wherein the second analog to digital conversion circuitry is configured to output a second digital signal to the second output line and the third analog to digital conversion circuitry is configured to output a third digital signal to the first output line.
8. The imaging device according to claim 7 , wherein the third digital signal is based on at least one of the second pixel signal or the third pixel signal.
9. The imaging device according to claim 7 , wherein the second digital signal is based on at least one of the second pixel signal or the third pixel signal.
10. The imaging device according to claim 1 , wherein the first signal line and the second signal line extend in a first direction.
11. The imaging device according to claim 10 , wherein the first output line and the second output line extend in a second direction which is perpendicular to the first direction.
12. The imaging device according to claim 1 , wherein the first analog to digital conversion circuitry comprises a first counter and a first memory and the second analog to digital conversion circuitry comprises a second counter and a second memory.
13. The imaging device according to claim 1 , wherein the first, second, third and fourth signal lines extend in a first direction.
14. The imaging device according to claim 13 , wherein the first and second output lines extend in a second direction which is perpendicular to the first direction.
15. A light detecting device, comprising:
a first pixel that outputs a first pixel signal;
a second pixel that outputs a second pixel signal;
a third pixel that outputs a third pixel signal;
a fourth pixel that outputs a fourth pixel signal;
a first signal line coupled to the first pixel;
a second signal line coupled to the second pixel;
a third signal line coupled to the third pixel;
a fourth signal line coupled to the fourth pixel;
first analog to digital conversion circuitry, a first input of the first analog to digital conversion circuitry being coupled to the first signal line;
second analog to digital conversion circuitry, a second input of the second analog to digital conversion circuitry being coupled to a first switch circuitry;
third analog to digital conversion circuitry, a third input of the third analog to digital conversion circuitry being coupled to a second switch circuitry;
fourth analog to digital conversion circuitry, a fourth input of the fourth analog to digital conversion circuitry being coupled to the fourth signal line;
a first output line coupled to a first output of the first analog to digital conversion circuitry and a third output of the third analog to digital conversion circuitry;
a second output line coupled to a second output of the second analog to digital conversion circuitry and a fourth output of the fourth analog to digital conversion circuitry;
wherein the first switch circuitry is configured to couple the second signal line to the second analog to digital conversion circuitry and couple the third signal line to the second analog to digital conversion circuitry selectively,
wherein the second switch circuitry is configured to couple the third signal line to the third analog to digital conversion circuitry and couple the second signal line to the third analog to digital conversion circuitry selectively,
wherein the first switch circuitry and second switch circuitry form an integrated switching pair, the integrated switching pair is provided between the second and, third pixels and the second and third analog to digital conversion circuitries,
wherein when the integrated switching pair operates in a first mode, the first, second, third and fourth pixel signals are converted to digital signals by the first, second, third and fourth analog to digital conversion circuitries, respectively,
wherein when the integrated switching pair operates in a second mode, the first and third pixel signals are converted to digital signals by the first and second analog to digital conversion circuitries, respectively, and the second and fourth pixel signals are converted to digital signals by the third and fourth analog to digital conversion circuitries, and
wherein the first analog to digital conversion circuitry comprises a first comparator, the second analog to digital conversion circuitry comprises a second comparator, the third analog to digital conversion circuitry comprises a third comparator and the fourth analog to digital conversion circuitry comprises a fourth comparator.
16. The light detecting device according to claim 15 , wherein the first analog to digital conversion circuitry is not coupled to the second output line and the second analog to digital conversion circuitry is not coupled to the first output line.
17. The light detecting device according to claim 15 , wherein the first output line and the second output line are coupled to signal processing circuitry.
18. The light detecting device according to claim 15 , wherein the first output line and the second output line are coupled to digital adder circuitry.
19. The light detecting device according to claim 15 , further comprising reference signal generation circuitry coupled to the first analog to digital conversion circuitry and the second digital to analog conversion circuitry.
20. The light detecting device according to claim 15 , wherein the first analog to digital conversion circuitry is configured to output a first digital signal to the first output line and the fourth analog to digital conversion circuitry is configured to output a fourth digital signal to the second output line.
21. The light detecting device according to claim 20 , wherein the second analog to digital conversion circuitry is configured to output a second digital signal to the second output line and the third analog to digital conversion circuitry is configured to output a third digital signal to the first output line.
22. The light detecting device according to claim 21 , wherein the third digital signal is based on at least one of the second pixel signal or the third pixel signal.
23. The light detecting device according to claim 21 , wherein the second digital signal is based on at least one of the second pixel signal or the third pixel signal.
24. The light detecting device according to claim 15 , wherein the first signal line and the second signal line extend in a first direction.
25. The light detecting device according to claim 24 , wherein the first output line and the second output line extend in a second direction which is perpendicular to the first direction.
26. The light detecting device according to claim 15 , wherein the first analog to digital conversion circuitry comprises a first counter and a first memory and the second analog to digital conversion circuitry comprises a second counter and a second memory.
27. The light detecting device according to claim 15 , wherein the first, second, third and fourth signal lines extend in a first direction.
28. The light detecting device according to claim 27 , wherein the first and second output lines extend in a second direction which is perpendicular to the first direction.