IP Library › Granted Patent US 10,770,128
Granted Patent B2
US 10,770,128 · App. 16/147,446 · Granted Sep 8, 2020

Non volatile mass storage device with improved refresh algorithm

Inventors: Mark Anthony Golez (Folsom, CA); David J. Pelster (Longmont, CO); Xin Guo (San Jose, CA); Paul D. Ruby (Folsom, CA)
Assignee: Intel Corporation
G11C11/40611G11C11/40603G11C11/40618G11C13/0023G11C13/0033G11C13/0061G11C16/08G11C16/32G11C16/349G11C16/3418G11C8/12G11C2211/4063
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Quick Facts
Patent No.
US 10,770,128
App. No.
16/147,446
Granted
Sep 8, 2020
Kind
B2
Abstract

A refreshing method is described. The method includes recognizing a set of blocks of a non-volatile memory for refreshing and then refreshing a subset of the data within the blocks, where, invalid data within the blocks is not recognized for refreshing and a group of blocks whose oldest data has not aged for a pre-set time period is not recognized for refreshing.

Claims (35)

1. An apparatus, comprising:

a controller to implement a non-volatile memory refresh algorithm, the controller comprising logic circuitry to recognize a set of blocks of the non-volatile memory for refreshing and then refresh only a subset of data stored within the set of blocks, where, invalid data is not recognized for refreshing and a group of blocks whose oldest data has not aged for a pre-set time period is not recognized for refreshing.

2. The apparatus of claim 1 wherein blocks of a same band are grouped together for recognition of refreshing and wherein valid data of the blocks within the same band are refreshed over time as a unit.

3. The apparatus of claim 2 wherein a next band's blocks do not begin to be refreshed until a previous band's blocks have been fully refreshed.

4. The apparatus of claim 1 wherein data invalidity/validity is tracked at a granularity that is less than or equal to a block.

5. The apparatus of claim 1 wherein the pre-set time period is programmable.

6. The apparatus of claim 1 wherein the non-volatile memory refresh algorithm determines a refresh rate as an amount of valid data recognized for refresh normalized by an expiration time less the pre-set time period.

7. The apparatus of claim 6 wherein the non-volatile memory refresh algorithm determines respective refresh rates for multiple bands having blocks recognized for refresh and combines the respective refresh rates to determine a refresh rate to be applied to a particular one of the multiple bands.

8. The apparatus of claim 1 wherein the controller is to persist, as part of a power down process of a non-volatile mass storage device, any of:

a hold-off period;

a maximum permitted time window without refresh; and,

timer values for different groups of blocks.

9. The apparatus of claim 1 wherein more than one group of blocks whose ageing is tracked as a single unit are concurrently refreshed.

10. A computing system, comprising:

a plurality of processing cores;

a system memory;

a memory controller disposed between the system memory and the plurality of processing cores;

a peripheral controller coupled to the memory controller;

a non volatile mass storage device comprising a controller to implement a non-volatile memory refresh algorithm, the controller comprising logic circuitry to recognize a set of blocks of the non-volatile memory for refreshing and then refresh only a subset of data stored within the set of blocks, where, invalid data is not recognized for refreshing and a group of blocks whose oldest data has not aged for a pre-set time period is not recognized for refreshing.

11. The computing system of claim 10 wherein blocks of a same band are grouped together for recognition of refreshing and wherein valid data of the blocks within the same band are refreshed over time as a unit.

12. The computing system of claim 11 wherein a next band's blocks do not begin to be refreshed until a previous band's blocks have been fully refreshed.

13. The computing system of claim 10 wherein data invalidity/validity is tracked at a granularity that is less than or equal to a block.

14. The computing system of claim 10 wherein the pre-set time period is programmable.

15. The computing system of claim 10 wherein the non-volatile memory refresh algorithm determines a refresh rate as an amount of valid data recognized for refresh normalized by an expiration time less the pre-set time period.

16. A machine readable medium having stored thereon instructions that when processed by a processor causes a refresh method to be performed, the refresh method comprising:

recognizing a set of blocks of a non-volatile memory for refreshing and then refreshing a subset of data within the set of blocks, where, invalid data within the set of blocks is not recognized for refreshing and a group of blocks whose oldest data has not aged for a pre-set time period is not recognized for refreshing.

17. The machine readable medium of claim 16 further comprising grouping blocks of a same band together for recognition of refreshing and refreshing valid data within the blocks of the same band over time as a unit.

18. The machine readable medium of claim 17 further comprising not beginning to refresh a next band's blocks until a previous band's blocks have been fully refreshed.

19. The machine readable medium of claim 16 wherein the method further comprises persisting, as part of a power down process of a non-volatile mass storage device, any of:

a hold-off period;

a maximum permitted time window without refresh; and,

timer values for different groups of blocks.

20. The machine readable medium of claim 16 wherein the pre-set time period is programmable.

21. The machine readable medium of claim 16 wherein the method further comprises determining a refresh rate as a number of blocks recognized for refresh normalized by an expiration time less the pre-set time period.

22. The machine readable medium of claim 16 wherein more than one group of blocks whose ageing is tracked as a single unit are concurrently refreshed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2018
From: GOLEZ, MARK ANTHONY; PELSTER, DAVID J.; GUO, XIN; RUBY, PAUL D.
To: INTEL CORPORATION
Reel/Frame 047514/0666 →
Continuity (1)
Related Publication 20190043556A1 · Feb 7, 2019