Integrated standard cell structure

1. An integrated circuit, comprising:

a first standard cell having a first p-type field-effect transistor (pFET) and a first n-type field-effect transistor (nFET) integrated, and having a first dielectric gate on a first standard cell boundary;

a second standard cell being adjacent to the first standard cell, having a second pFET and a second nFET integrated, and having a second dielectric gate on a second standard cell boundary; and

a first filler cell configured between the first and second standard cells, and spanning between the first dielectric gate and the second dielectric gate, wherein

the first pFET and the second pFET are formed on a first continuous active region, and

the first nFET and the second nFET are formed on a second continuous active region.

2. The integrated circuit of claim 1 , further comprising:

a third dielectric gate and a fourth dielectric gate, wherein

the first standard cell spans between the first dielectric gate and the third dielectric gate along a first direction, and

the second standard cell spans between the second dielectric gate and the fourth dielectric gate along the first direction.

3. The integrated circuit of claim 2 , wherein

each of the first continuous active region and the second continuous active region extends through the first standard cell, the first filler cell, and the second standard cell, and

each of the first, second, third and fourth dielectric gates extends from the first continuous active region to the second continuous active region.

4. The integrated circuit of claim 3 , wherein

the first filler cell spans a one-pitch dimension P from the first dielectric gate to the second dielectric gate along the first direction;

the first standard cell spans a first dimension D 1 from the third dielectric gate to the first dielectric gate along the first direction; and

the second standard cell spans a second dimension D 2 from the second dielectric gate to the fourth dielectric gate along the first direction, wherein D 2 =D 1 >2*P.

5. The integrated circuit of claim 3 , wherein

the first standard cell further includes a first gate stack extending from the first continuous active region to the second continuous active region along a second direction being orthogonal to the first direction; and

the second standard cell further includes a second gate stack extending from the first continuous active region to the second continuous active region along the second direction.

6. The integrated circuit of claim 5 , wherein the first filler cell further includes a third gate stack disposed between the first and second dielectric gates, and extends over from the first continuous active region to the second continuous active region along the second direction,

the first gate stack is interposed between the first dielectric gate and the third dielectric gate;

the second gate stack is interposed between the second dielectric gate and the fourth dielectric gate; and

the third gate stack is interposed between the first dielectric gate and the second dielectric gate.

7. The integrated circuit of claim 5 , wherein

the first standard cell further includes a third gate stack directly on the first continuous active region and a fifth dielectric gate on the second continuous active region, wherein the third gate stack extends along the second direction to contact the fifth dielectric gate; and

the second standard cell further includes a sixth dielectric gate on the first continuous active region and a fourth gate stack directly on the second continuous active region, wherein the sixth dielectric gate extends along the second direction to contact the fourth gate stack.

8. The integrated circuit of claim 5 , wherein

the first standard cell further includes a third gate stack directly on the first continuous active region and a fifth dielectric gate on the second continuous active region, wherein the third gate stack extends along the second direction to contact the fifth dielectric gate; and

the second standard cell further includes a sixth dielectric gate on the second continuous active region and a fourth gate stack directly on the first continuous active region, wherein the sixth dielectric gate extends along the second direction to contact the fourth gate stack.

9. The integrated circuit of claim 2 , further comprising

a third standard cell having a third pFET and a third nFET integrated, and having a fifth dielectric gate on a third standard cell boundary; and

a second filler cell configured between the second and third standard cells, wherein

the second filler cell spans from the fourth dielectric gate to a sixth dielectric gate on a third filler cell boundary,

the third pFET is formed on the first continuous active region,

the third nFET is formed on the second continuous active region, and

the third standard cell adjoins the second filler cell on the sixth dielectric gate.

10. The integrated circuit of claim 1 , wherein the first filler cell further includes a gate stack interposed between and spaced equally from the first dielectric gate and the second dielectric gate, wherein the gate stack extends from the first continuous active region to the second continuous active region.

11. An integrated circuit, comprising:

a first standard cell having a first gate stack, a second gate stack, a first dielectric gate on a first standard cell boundary, and a second dielectric gate contacting the second gate stack;

a second standard cell having a third gate stack, a fourth gate stack, a third dielectric gate on a second standard cell boundary, and a fourth dielectric gate contacting the fourth gate stack;

a first continuous active region extending through the first standard cell and the second standard cell; and

a second continuous active region extending through the first standard cell and the second standard cell, wherein each of the first gate stack, the third gate stack, the first dielectric gate, and the third dielectric gate is extending from the first continuous active region to the second continuous active region.

12. The integrated circuit of claim 11 , further comprising a first filler cell disposed between the first and second standard cells, and spanning a one-pitch dimension P from a fifth dielectric gate and a sixth dielectric gate along a first direction, wherein the first standard cell spans a first dimension D 1 from the first dielectric gate to the fifth dielectric gate along the first direction; and

the second standard cell spans a second dimension D 2 from the third dielectric gate to the sixth dielectric gate along the first direction, wherein D 2 =D 1 >2*P.

13. The integrated circuit of claim 11 , wherein

the second gate stack and the fourth dielectric gate are formed directly on the first continuous active region; and

the second dielectric gate and the fourth gate stack are formed directly on the second continuous active region.

14. The integrated circuit of claim 11 , wherein

the second gate stack and the fourth gate stack are formed directly on the first continuous active region; and

the second dielectric gate and the fourth dielectric gate are formed directly on the second continuous active region.

15. The integrated circuit of claim 11 , wherein the first standard cell adjoins the second standard cell on a fifth dielectric gate extending over from the first continuous active region to the second continuous active region.

16. The integrated circuit of claim 11 , wherein

the second and fourth dielectric gates are disposed on the first continuous active region; and

the second and fourth gate stacks are disposed on the second continuous active region.

17. The integrated circuit of claim 11 , wherein

the second dielectric gate and the fourth gate stack are disposed on the first continuous active region; and

the fourth dielectric gate and the second gate stack are disposed on the second continuous active region.

18. An integrated circuit, comprising:

a first standard cell having a first gate stack, and having a first dielectric gate on a first standard cell boundary;

a second standard cell being adjacent to the first standard cell, having a second gate stack, and having a second dielectric gate on a second standard cell boundary;

a first filler cell configured between the first and second standard cells, and spanning from the first dielectric gate to the second dielectric gate;

a first continuous active region extending through the first standard cell, the first filler cell and the second standard cell along a first direction; and

a second continuous active region extending through the first standard cell, the first filler cell and the second standard cell along the first direction, wherein each of the first gate stack, the second gate stack, the first dielectric gate and the second dielectric gate is extended from a first continuous active region to a second continuous active region.

19. The integrated circuit of claim 18 , wherein

the first standard cell further includes a third gate stack and a third dielectric gate being aligned with and contacting the third gate stack; and

the second standard cell further includes a fourth gate stack and a fourth dielectric gate being aligned with and contacting the fourth gate stack.

20. The integrated circuit of claim 18 , wherein

the first filler cell adjoins the first standard cell on the first dielectric gate and adjoins the second standard cell on the second dielectric gate;

the first continuous active region is enclosed in an n-type doped well; and

the second continuous active region is enclosed in a p-type doped well.