Static random access memory
An SRAM cell includes two inverters and three transistors. The first inverter includes a first end coupled to a first storage node and a second end coupled to a second storage node. The second inverter includes a first end coupled to the second storage node and a second end coupled to the first storage node. The first transistor includes a first end coupled to the first storage node, a second end and a control end. The second transistor includes a first end coupled to the second end of the first transistor, a second end coupled to a first bit line, and a control end. The third transistor includes a first end coupled between the second end of the first transistor and the first end of the second transistor, a second end, and a control end coupled to the first storage node.
1. A static random-access memory (SRAM) cell, comprising:
a first inverter, comprising:
a first end coupled to a first storage node; and
a second end coupled to a second storage node;
a second inverter, comprising:
a first end coupled to the second storage node; and
a second end coupled to the first storage node;
a first transistor, comprising:
a first end coupled to the first storage node;
a second end; and
a control end;
a second transistor, comprising:
a first end coupled to the second end of the first transistor;
a second end coupled to a first bit line; and
a control end; and
a third transistor, comprising:
a first end coupled between the second end of the first transistor and the first end of the second transistor;
a second end; and
a control end coupled to the first storage node, wherein a doping type of the second transistor is different from a doping type of the third transistor.
2. The SRAM cell of claim 1 , wherein a doping type of the first transistor is the same as a doping type of the second transistor.
3. The SRAM cell of claim 1 , wherein:
the first transistor and the second transistor have a first doping type;
the third transistor has a second doping type; and
the first doping type is different from the second doping type.
4. The SRAM cell of claim 1 , wherein:
the control end of the second transistor is coupled to a first word line;
the control end of the first transistor is coupled to a second word line; and
the first word line is disposed to be perpendicular to the second word line.
5. The SRAM cell of claim 1 , further comprising:
a fourth transistor, comprising:
a first end coupled to the second storage node;
a second end; and
a control end coupled to the control end of the first transistor;
a fifth transistor, comprising:
a first end coupled to the second end of the fourth transistor;
a second end coupled to a second bit line; and
a control end coupled to the control end of the second transistor; and
a sixth transistor, comprising:
a first end coupled between the second end of the fourth transistor and the first end of the fifth transistor;
a second end coupled to the second end of the third transistor; and
a control end coupled to the second storage node.
6. The SRAM cell of claim 5 , wherein:
a doping type of the fifth transistor is different from a doping type of the sixth transistor.
7. The SRAM cell of claim 5 , wherein:
a doping type of the first transistor is the same as a doping type of the second transistor; and
a doping type of the fourth transistor is the same as a doping type of the fifth transistor.
8. The SRAM cell of claim 5 , wherein:
the first transistor, the second transistor, the fourth transistor and the fifth transistor have a first doping type;
the third transistor and the sixth transistor have a second doping type; and
the first doping type is different from the second doping type.
9. The SRAM cell of claim 5 , wherein:
the control end of the second transistor and the control end of the fifth transistor are coupled to a first word line;
the control end of the first transistor and the control end of the fourth transistor are coupled to a second word line; and
the first word line is disposed to be perpendicular to the second word line.