Fast, energy efficient 6T SRAM arrays using harvested data
CMOS harvesting circuits are disclosed for conventional 6T SRAM bitcell arrays enabling substantial improvements to SRAM access time, pipeline performance and to SRAM active and leakage energy consumption—without scaling operating voltages while also improving Read and Write margins using assist schemes at very low area and energy overhead by reusing circuits that harvest charge. Active energy dissipation during an SRAM read access is lowered by use of novel sensing schemes that self-limit signal development on the BL without the energy overheads seen in conventional designs from sense-amp offsets, BL column leakage and uncertain read current. Improvements in access time are enabled by increasing the signal development rate on the BL—by comparing the rising electric potential of harvested charge with a decreasing BL voltage in a bitcell column using a novel and compact inverting amplifier with dynamic reset. This area and energy efficient scheme leveraging availability of harvested charge not only self-limits signal development on the BL to lower active power and improve read latency, but also eliminates most of the uncertainty of BL voltage signal from uncertain read current by using a capacitive divider. Charge harvested in each column of bitcells from a read/write access is moved to a local harvest grid with a fraction of the capacitance of the BLs accessed in the subarray, at a voltage closer to V DD and is readily tapped into during a following Write access lowering write energy consumption from the power grid by over 30%. Active or standby mode leakage is lowered by the raised voltage of the harvesting node in each column—that is discharged only before the WL selects—for all columns during a Read and for half-select columns during a Write.
1. A transistor memory device, comprising:
a plurality of transistor storage elements that share a common source or ground terminal, the common source or ground terminal (1) reset to a reference ground potential of the transistor memory device directly before a read data access and a write data access and (2) electrically decoupled from the reference ground potential of the transistor memory device during the read data access and during the write data access.
2. The transistor memory device of claim 1 , wherein the plurality of transistor storage elements that share the common source or ground terminal store charge on a collective capacitance includes (1) a total capacitance of the common source or ground terminal, the common source or ground terminal connected to each other identified as a harvest node and (2) a capacitance of a storage node in a transistor storage element from the plurality of transistor storage elements, each transistor storage element from the plurality of transistor storage elements including a word line port configured to select (a) a transistor storage element from the plurality of transistor storage elements and (b) at least one bitline, each transistor storage element from the plurality of transistor storage elements configured to perform (i) the read data access from or (ii) the write data access to that transistor storage element, the harvest node configured to store a harvested charge transferred from the selected bitline to increase an output voltage at the harvest node during the read data access or the write data access, the harvest node electrically coupled to a harvest circuit.
3. The transistor memory device of claim 2 , further comprising:
a capacitive divider electrically connected between the selected bitline and the harvest node, the capacitive divider configured to increase a voltage swing on the harvest node within a predefined limit to retain data in all transistor storage elements from the plurality of transistor storage elements except in transistor storage elements from the plurality of transistor storage elements selected for a write data access, the capacitive divider configured to maximize an increase in an electric potential the harvest node will rise to during the read data access or the write data access to (i) increase an effective signal development rate as a voltage difference between selected bitline and the harvest node, with less read current (ii) lower active and leakage energy during the read data access or the write data access or (iii) reduce an uncertainty in voltage signal development on the selected bitline and the harvest node during the read data access.
4. The transistor memory device of claim 2 wherein:
the collective capacitance is determined by and proportional to (1) a number of transistor storage elements from the plurality of transistor storage elements that share the common source or ground terminal and (2) the storage node capacitance of the selected transistor storage element,
a bitline capacitance determined by and proportional to a number of transistor storage elements from a plurality of transistor storage elements shared by a common bitline.
5. The transistor memory device of claim 3 wherein the selected bitline is configured to be pre-charged to a voltage less than a voltage source coupled to a supply voltage terminal of a plurality of transistor storage elements shared by a common bitline.
6. The transistor memory device of claim 3 wherein the selected bitline is configured to be pre-charged to a voltage equal to a voltage source coupled to a supply voltage terminal of a plurality of transistor storage elements shared by a common bitline.
7. The transistor memory device of claim 6 wherein the capacitive divider between the collective capacitance and a bitline capacitance is configured to maximize an increase in the electric potential of the harvest node during the read data access or the write data access.
8. The transistor memory device of claim 3 wherein the harvest circuit includes an inverter with two parallel NFET footer devices in parallel to a PFET footer device with a gate input of the inverter is electrically connected to the common bitline and a source terminal of the inverter electrically is connected to the harvest node.
9. The transistor memory device of claim 8 wherein the harvest circuit is activated with a first active high pulse and a second active high pulse that does not overlap with the first active high pulse and that drive gate inputs of a first parallel NFET footer device from the two parallel NFET footer devices and a second parallel NFET footer device from the two parallel NFET footer devices, respectively, directly before the read data access or the write data access.
10. The transistor memory device of claim 9 wherein a first NFET footer device whose drain terminal is connected to the harvest node and whose source terminal is connected to a harvest grid, is enabled by an active high pulse at a gate input of the first NFET footer to transfer charge from the harvest node to the harvest grid while lowering the electric potential of the harvest node to equal a rising electric potential of the harvest grid, the harvest grid including a network of capacitors from metal wiring included in transistor memory device, it's a harvest grid configured to accumulate charge from a plurality of harvest nodes that includes the harvest node included in the transistor memory device.
11. The transistor memory device of claim 10 wherein a second NFET footer device whose drain terminal is connected to the harvest node and whose source terminal is connected to a reference ground terminal of the transistor memory device, is enabled by a second active high pulse at a gate input of the second NFET footer device that is non-overlapping with and directly follows a first active high pulse discharging a remainder of charge held at the harvest node to the reference ground terminal of the transistor memory device bringing the electric potential of the harvest node to equal the reference ground electric potential of the transistor memory device directly before the read data access or the write data access.
12. The transistor memory device of claim 11 wherein the harvest circuit responds to the read data access with a word line selecting a subset of transistor storage elements from the plurality of transistor storage elements such that charge on each precharged bitline coupled to the subset of transistor storage elements is shared through and by the subset of transistor storage elements with the harvest node associated with the subset of transistor storage element, the plurality of harvest nodes coupled to the subset of transistor storage elements being reset to the reference ground potential of the transistor memory device before the word line selects the subset of transistor storage elements for the read data access.
13. The transistor memory device of claim 11 wherein a PFET device in parallel to the first NFET footer device and the second NFET footer device is configured to operate as a diode and bleed away charge from the harvest node during a predetermined period of inactivity.
14. The transistor memory device of claim 7 wherein a decreasing electric potential of the selected bitline self-limits passage of the read current through the selected transistor storage element as a voltage difference between the decreasing electric potential of the selected bitline and a rising electric potential of the harvest node approaches a transistor threshold voltage at which point the selected transistor storage element self-disables passage of the read current even if the transistor storage element is still selected by a word line enabling uncertainty of voltage signal on the selected bitline to be mostly eliminated.
15. The transistor memory device of claim 8 , wherein an increasing electric potential of the harvest node causes a logic threshold voltage of the inverter in the harvest circuit to rise enabling a smaller voltage drop on the selected bitline to trigger a transition at an output of the inverter of the harvest circuit sooner than in an inverter with a static logic threshold voltage.
16. The transistor memory device of claim 14 , wherein an increasing electric potential of the harvest node, electrically connected to a source terminal or a ground terminal of the plurality of transistor storage elements, an elevated electric potential of the harvest node lowers subthreshold leakage from access NFET transistors in unselected transistor storage elements that share a common harvest node with the selected transistor storage element, reverse biases substantially lowering a leakage noise currents from the unselected transistor storage elements.