Heterojunction devices and methods for fabricating the same
Current conducting devices and methods for their formation are disclosed. Described are vertical current devices that include a substrate, an n-type material layer, a plurality of p-type gates, and a source. The n-type material layer disposed on the substrate and includes a current channel. A plurality of p-type gates are disposed on opposite sides of the current channel. A source is disposed on a distal side of the current channel with respect to the substrate. The n-type material layer comprises beta-gallium oxide.
1. A vertical current conducting device, comprising:
an n+ beta-gallium oxide layer;
an n− beta-gallium oxide layer disposed on the n+ beta-gallium oxide layer, wherein the n− beta-gallium oxide layer includes a current channel;
a plurality of p-type gates disposed on opposite sides of the current channel;
a plurality of p-type terminations disposed on a side of the n− beta gallium oxide layer that is distal from the n+ beta-gallium oxide layer; and
a source disposed on a distal side of the current channel with respect to the n+ beta-gallium oxide layer.
2. The device according to claim 1 , further comprising:
a plated copper layer substrate, wherein the n+ beta-gallium oxide layer is disposed on the plated copper layer substrate.
3. The device according to claim 2 , wherein the plated copper layer substrate is directly bonded to the n+ beta gallium oxide layer.
4. The device according to claim 1 , further comprising:
a plurality of nucleation layers respectively corresponding to the plurality of p-type terminations, wherein each nucleation layer is provided between the corresponding p-type termination and the n− beta-gallium oxide layer.
5. The device according to claim 4 , further comprising:
wherein the plurality of p-type gates comprise diamond, the plurality of p-type terminations comprise diamond, and the plurality of nucleation layers are diamond nucleation layers.
6. The device according to claim 1 , wherein when a forward bias is applied to the plurality of p-type gates, charge carriers in the current channel enter a conduction band.
7. The device according to claim 6 , wherein when a reverse bias is applied to the plurality of p-type gates, charges carriers are depleted from the current channel.
8. The device according to claim 1 , further comprising:
at least one nucleation layer provided between the current channel and each of the plurality of p-type gates.
9. The device according to claim 8 , further comprising:
a wideband gap oxide layer disposed between the nucleation layer and each of the plurality of p-type gates.
10. The device according to claim 1 , wherein the plurality of p-type gates are L-shaped.
11. The device according to claim 1 , wherein a thickness of the current channel and the source is substantially the same as a thickness of the plurality of p-type gates in a direction perpendicular to the n+ beta-gallium oxide layer.
12. The device according to claim 1 , wherein the plurality of p-type gates are disposed at least partially within the n− beta-gallium oxide layer.
13. The device according to claim 12 , further comprising:
a plurality of nucleation layers respectively corresponding to the plurality of p-type gates, wherein each nucleation layer partially surrounds the corresponding p-type gate such that the p-type gates does not directly contact the n− beta-gallium oxide layer.
14. The device according to claim 1 , further comprising:
a plurality of nucleation layers respectively corresponding to the plurality of p-type terminations, wherein the plurality of p-type terminations are disposed at least partially within the n− beta-gallium oxide layer and each nucleation layer partially surrounds the corresponding p-type termination such that the p-type termination does not directly contact the n− beta-gallium oxide layer.
15. The device according to claim 1 , further comprising:
a plurality of ion-implanted regions,
wherein each of the plurality of ion-implanted regions is disposed adjacent to one of the plurality of p-type gates or one of the plurality of p-type terminations.