Metal gate transistor with a stacked double sidewall spacer structure
A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; forming a first contact etch stop layer (CESL) around the spacer; forming a mask layer on the first CESL; removing part of the mask layer; removing part of the first CESL; forming a second CESL on the mask layer and the gate structure; and removing part of the second CESL.
1. A semiconductor device, comprising:
a gate structure on a substrate, wherein the gate structure comprises a work function metal layer;
a spacer around the gate structure, wherein the spacer comprises:
an offset spacer comprising a L-shape around the gate structure; and
a main spacer comprising an I-shape on the offset spacer, wherein the offset spacer and the main spacer comprise dielectric materials;
a first contact etch stop layer (CESL) around the spacer and contacting the offset spacer and the main spacer directly; and
a second CESL around and directly contacting the main spacer and on the first CESL, wherein a bottommost surface of the second CESL being curved contacts a topmost surface of the first CESL directly forming a contacting surface therebetween of a curved surface and a bottommost surface of the first CESL contacts the substrate directly.
2. The semiconductor device of claim 1 , further comprising source/drain region in the substrate adjacent to two sides of the spacer, wherein the first CESL is disposed directly on the source/drain region in the substrate, and directly contacting a contact plug.
3. The semiconductor device of claim 1 , wherein the first CESL and the second CESL comprise different material.
4. The semiconductor device of claim 1 , wherein the first CESL and the second CESL comprise different dielectric constant.
5. The semiconductor device of claim 1 , wherein a dielectric constant of the first CESL is lower than a dielectric constant of the second CESL.
6. The semiconductor device of claim 1 , wherein the first CESL comprises silicon oxycarbonitride (SiOCN) and the second CESL comprises silicon nitride (SiN).
7. The semiconductor device of claim 1 , wherein the gate structure comprises a metal gate and a hard mask on the metal gate.
8. The semiconductor device of claim 7 , wherein a top surface of the first CESL is lower than a top surface of the metal gate.
9. The semiconductor device of claim 7 , further comprising an interlayer dielectric (ILD) layer around the gate structure, wherein the top surfaces of the ILD layer and the hard mask are coplanar.
10. The semiconductor device of claim 9 , wherein the top surfaces of the ILD layer and the second CESL are coplanar.