IP Library › Granted Patent US 10,778,920
Granted Patent B2
US 10,778,920 · App. 16/016,793 · Granted Sep 15, 2020

Photoelectric conversion apparatus and camera

Inventors: Takanori Yamashita (Hachioji, JP); Kazuhiro Saito (Tokyo, JP); Tatsuya Ryoki (Kawasaki, JP); Yoshikazu Yamazaki (Sagamihara, JP)
Assignee: Canon Kabushiki Kaisha
H04N5/37455H01L27/1461H01L27/14603H01L27/14612H01L27/14683H04N5/335H04N5/64
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Quick Facts
Patent No.
US 10,778,920
App. No.
16/016,793
Granted
Sep 15, 2020
Kind
B2
Abstract

A photoelectric conversion apparatus having a first substrate and a second substrate overlaid on each other and including electrically conductive portions is provided. The first substrate includes a photoelectric conversion element, a first portion configured to form part of a first surface, a second portion which is included in an electrically conductive pattern closest to the first portion, and a third portion which is included in an electrically conductive pattern second closest to the first portion. The second substrate includes a fourth portion configured to form part of a second surface, and a circuit. In a planar view with respect to the first surface, an area of the first portion is smaller than an area of the second portion and larger than an area of a portion of the third portion overlaying the second portion.

Claims (35)

1. A photoelectric conversion apparatus comprising:

a first semiconductor region in which a plurality of pixels are arranged, each pixel including a photoelectric conversion element;

a second semiconductor region in which a circuit is arranged, the circuit including at least one of a signal processing circuit configured to process a signal based on charges generated in the photoelectric conversion element or a control circuit configured to supply a control signal to the plurality of pixels; and

a plurality of connecting portions each including two electrically conductive portions in contact with each other and each electrically connecting the circuit and at least one of the plurality of pixels,

wherein the first semiconductor region, the two electrically conductive portions included in one of the plurality of connecting portions, and the second semiconductor region are arranged in such order along a first direction,

wherein the plurality of connecting portions include a first number, one or more, of first connecting portions forming a first electrical node, and

wherein the plurality of connecting portions include a second number, one or more, of second connecting portions forming a second electrical node, the second number being different from the first number and the second electrical node being electrically separated from the first electrical node.

2. The apparatus according to claim 1 , wherein the circuit includes the signal processing circuit,

wherein each of the plurality of pixels includes a transistor having a gate for receiving a signal based on charges generated in the photoelectrical conversion element, and

wherein the first electrical node is included in a signal path between the transistor and the signal processing circuit.

3. The apparatus according to claim 2 , wherein the first number is less than the second number.

4. The apparatus according to claim 2 , wherein the second number is less than the first number.

5. The apparatus according to claim 1 , wherein the circuit includes the control circuit, and

wherein the second electrical node is included in a signal path between the control circuit and one of the plurality of pixels.

6. The apparatus according to claim 5 , wherein the first number is less than the second number.

7. The apparatus according to claim 5 , wherein the second number is less than the first number.

8. The apparatus according to claim 1 , wherein the circuit includes the signal processing circuit and the control circuit,

wherein each of the plurality of pixels includes a transistor having a gate for receiving a signal based on charges generated in the photoelectrical conversion element,

wherein the first electrical node is included in a signal path between the transistor and the signal processing circuit, and

wherein the second electrical node is included in a signal path between the control circuit and one of the plurality of pixels.

9. The apparatus according to claim 8 , wherein the first number is less than the second number.

10. The apparatus according to claim 8 , wherein the second number is less than the first number.

11. The apparatus according to claim 1 , wherein each of the plurality of pixels includes a transistor having a gate for receiving the control signal supplied from the control circuit, and

wherein the first electrical node is included in a signal path between the transistor and the control circuit.

12. The apparatus according to claim 11 , wherein the first number is less than the second number.

13. The apparatus according to claim 11 , wherein the second number is less than the first number.

14. The apparatus according to claim 1 , wherein the plurality of connecting portions include at least two of the first connecting portions arranged in a second direction crossing the first direction, and

wherein an insulating member is arranged between the at least two of the first connecting portions.

15. The apparatus according to claim 1 , wherein the plurality of connecting portions include at least two of the second connecting portions arranged in a second direction crossing the first direction, and

wherein an insulating member is arranged between the at least two of the second connecting portions.

16. The apparatus according to claim 1 , wherein each of the plurality of connecting portions includes a first plug arranged between the respective connecting portion and the first semiconductor region and a second plug arranged between the respective connecting portion and the second semiconductor region, the first plug being in contact with one of the two electrically conductive portions and the second plug being in contact with the other of the two electrically conductive portions.

17. The apparatus according to claim 1 , further comprising:

a first electrically conductive pattern arranged between the plurality of connecting portions and the first semiconductor region and electrically connecting at least one of the plurality of connecting portions and at least one of the plurality of pixels; and

a second electrically conductive pattern arranged between the plurality of connecting portions and the second semiconductor region and electrically connecting at least one of the plurality of connecting portions and the circuit.

18. The apparatus according to claim 1 , wherein the signal processing circuit includes an analog/digital conversion circuit configured to convert a signal based on charges generated in the photoelectric conversion element into a digital signal.

Priority Claims (1)
JP 2016-131041 · Jun 30, 2016 · national
Continuity (2)
Continuation 15620972 · Jun 13, 2017
Related Publication 20180309950A1 · Oct 25, 2018
Cited By (3)
US 12,335,651 US 12,389,139 US 12,739,526