Systems, methods, and apparatus for combatting direct memory access attacks
A data processing system includes technology to detect a memory attack. The data processing system comprises a processing core, a memory controller, a memory bus, and memory. The memory controller comprises a memory attack detection module (MADM). The MADM comprises first and second input units and control logic in communication with the first and second input units. The control logic is configured to determine, based on first and second signals from the first and second input units, respectively, whether the memory bus is carrying a clock enable (CKE) signal of high (H), even though the memory controller is generating the CKE signal of low (L). The control logic is also configured to generate a physical memory attack detection indicator that indicates whether the memory bus is carrying the CKE signal of H, even though the memory controller is generating the CKE signal of L. Other embodiments are described and claimed.
1. A semiconductor package with technology to detect a memory attack, the semiconductor package comprising:
an integrated circuit comprising a memory attack detection module (MADM), wherein the MADM comprises:
a first input unit;
a second input unit; and
control logic in communication with the first input unit and the second input unit, wherein the control logic is configured to:
determine, based on a first signal from the first input unit and a second signal from the second input unit, whether a memory bus in a data processing system is carrying a clock enable (CKE) signal of high (H), even though a memory controller in the data processing system is generating the CKE signal of low (L); and
generate a physical memory attack detection (PMAD) indicator, wherein the PMAD indicator indicates whether the memory bus is carrying the CKE signal of H, even though the memory controller is generating the CKE signal of L.
2. A data processing system comprising:
a semiconductor package according to claim 1 ;
a memory bus according to claim 1 ; and
memory coupled to the memory bus;
wherein the data processing system is configured to automatically take at least one remedial measure in response to a positive PMAD indicator; and
wherein the at least one remedial measure comprises at least one action from the group consisting of:
waking up the data processing system;
causing the data processing system to reboot; and
shutting off power to the memory.
3. A data processing system comprising:
a semiconductor package according to claim 1 ;
a memory bus according to claim 1 ; and
memory coupled to the memory bus;
wherein the data processing system is configured to automatically display a PMAD notice, in response to a positive PMAD indicator.
4. A data processing system comprising:
a semiconductor package according to claim 1 ;
a memory bus according to claim 1 ;
memory coupled to the memory bus;
a processing core in communication with the memory controller;
a power management unit (PMU) in communication with the memory controller; and
a manageability engine (ME) in communication with the memory controller, and wherein:
the integrated circuit comprises the memory controller;
the memory controller comprises the MADM;
the MADM is configured to generate the PMAD indicator by causing a PMAD register in the data processing system to be set with the PMAD indicator; and
the PMAD register comprises at least one register in at least one component from the group consisting of the memory controller, the PMU and the ME.
5. A semiconductor package according to claim 1 , wherein the MADM is configured to generate the PMAD indicator by performing at least one action from the group consisting of:
sending the PMAD indicator as a signal on an output unit of the MADM; and
causing a PMAD register in the data processing system to be set with the PMAD indicator.
6. A semiconductor package according to claim 1 , wherein:
the integrated circuit comprises the memory controller;
the memory controller comprises the MADM;
the memory controller comprises the PMAD register; and
the MADM is configured to generate the PMAD indicator by causing the PMAD register to be set with the PMAD indicator.
7. A semiconductor package according to claim 1 , wherein:
the integrated circuit comprises the memory controller;
the memory controller comprises the MADM;
the memory controller comprises a PMAD register; and
the MADM is configured to generate the PMAD indicator by causing the PMAD register in the memory controller to be set with the PMAD indicator.
8. A semiconductor package according to claim 1 , wherein:
the integrated circuit comprises the memory controller;
the memory controller comprises the MADM;
the semiconductor package further comprises a processing core, a power management unit (PMU), and a manageability engine (ME) in communication with the memory controller;
the MADM is configured to generate the PMAD indicator by causing a PMAD register in the data processing system to be set with the PMAD indicator; and
the PMAD register comprises at least one register in at least one component from the group consisting of the memory controller, the PMU and the ME.
9. A data processing system with technology to detect a memory attack, the data processing system comprising:
a processing core;
a memory controller in communication with the processing core;
a memory bus in communication with the memory controller;
memory in communication with the memory bus; and
a memory attack detection module (MADM) in the memory controller, wherein the MADM comprises:
a first input unit;
a second input unit; and
control logic in communication with the first input unit and the second input unit, wherein the control logic is configured to:
determine, based on a first signal from the first input unit and a second signal from the second input unit, whether the memory bus is carrying a clock enable (CKE) signal of high (H), even though the memory controller is generating the CKE signal of low (L); and
generate a physical memory attack detection (PMAD) indicator, wherein the PMAD indicator indicates whether the memory bus is carrying the CKE signal of H, even though the memory controller is generating the CKE signal of L.
10. A data processing system according to claim 9 , wherein:
the data processing system is configured to automatically take at least one remedial measure in response to a positive PMAD indicator; and
the at least one remedial measure comprises at least one action from the group consisting of:
waking up the data processing system;
causing the data processing system to reboot; and
shutting off power to the memory.
11. A data processing system according to claim 9 , wherein the data processing system is configured to automatically display a PMAD notice, in response to a positive PMAD indicator.
12. A data processing system according to claim 9 , wherein the MADM is configured to generate the PMAD indicator by performing at least one action from the group consisting of:
sending the PMAD indicator as a signal on an output unit of the MADM; and
causing a PMAD register in the data processing system to be set with the PMAD indicator.
13. A data processing system according to claim 9 , wherein:
the memory controller comprises a PMAD register; and
the MADM is configured to generate the PMAD indicator by causing the PMAD register in the memory controller to be set with the PMAD indicator.
14. A data processing system according to claim 9 , further comprising:
a power management unit (PMU) in communication with the memory controller; and
a manageability engine (ME) in communication with the memory controller, and wherein:
the MADM is configured to generate the PMAD indicator by causing a PMAD register in the data processing system to be set with the PMAD indicator; and
the PMAD register comprises at least one register in at least one component from the group consisting of the memory controller, the PMU and the ME.
15. A method for detecting a memory attack, the method comprising:
at a memory attack detection module (MADM) of a data processing system, automatically determining, based on a first signal and a second signal, whether a memory bus in the data processing system is carrying a clock enable (CKE) signal of high (H), even though a memory controller in the data processing system is generating the CKE signal of low (L); and
generating a physical memory attack detection (PMAD) indicator, wherein the PMAD indicator indicates whether the memory bus is carrying the CKE signal of H, even though the memory controller is generating the CKE signal of L.
16. A method according to claim 15 , further comprising:
automatically taking at least one remedial measure in response to a positive PMAD indicator, wherein the at least one remedial measure comprises at least one action from the group consisting of:
waking up the data processing system;
causing the data processing system to reboot; and
shutting off power to the memory.
17. A method according to claim 15 , further comprising:
automatically displaying a PMAD notice, in response to a positive PMAD indicator.
18. A method according to claim 15 , wherein the MADM generates the PMAD indicator by causing a PMAD register in the memory controller to be set with the PMAD indicator.
19. A method according to claim 15 , wherein:
the MADM generates the PMAD indicator by causing a PMAD register in the data processing system to be set with the PMAD indicator; and
the PMAD register comprises at least one register in at least one component from the group consisting of the memory controller, a power management unit (PMU) in communication with the memory controller, and a manageability engine (ME) in communication with the memory controller.
20. A method according to claim 15 , wherein the MADM generates the PMAD indicator by performing at least one action from the group consisting of:
sending the PMAD indicator as a signal on an output unit of the MADM; and
causing a PMAD register in the data processing system to be set with the PMAD indicator.