Castellated superjunction transistors

1. A transistor comprising:

a source region overlying a base structure;

a drain region overlying the base structure;

a block of semiconducting material overlying the base structure and being disposed between the source region and the drain region, the block of semiconducting material comprising;

a gate controlled region adjacent the source region; and

a drain access region disposed between the gate controlled region and the drain region, the drain access region being formed of a plurality of semiconducting material ridges spaced apart from one another by non-channel trench openings, wherein at least a portion of the non-channel trench openings being filled with a doped material to provide a depletion region to improve breakdown voltage of the transistor.

2. The transistor of claim 1 , wherein the doped material is boron p-doped diamond.

3. The transistor of claim 1 , wherein the doped material is Mg- or Ca-doped GaN.

4. The transistor of claim 1 , further comprising a gate contact that extends over the gate controlled region to control current flowing in the block of semiconductor material between the source region and the drain region.

5. The transistor of claim 1 , further comprising a top portion of doped material that shorts together the doped material in each non-channel trench opening to collectively form a superjunction with the plurality of semiconducting material ridges in the drain access region.

6. The transistor of claim 1 , further comprising a source contact disposed over the source region and a drain contact disposed over the drain region, wherein the source region and the drain region are formed of n+ doped gallium nitride.

7. The transistor of claim 1 , further comprising a diamond passivation layer overlying the source region, the drain region, the gate contact and the drain access region.

8. The transistor of claim 1 , wherein the transistor is a super-lattice castellated gate heterojunction field effect transistor (SLCFET).

9. The transistor of claim 8 , wherein the gate controlled region is formed of semiconducting material ridges spaced apart from one another by non-channel trench openings, and each of the semiconductor material ridges are formed a plurality of heterostructures that each form a portion of a parallel channel of the transistor.

10. The transistor of claim 9 , further comprising a gate contact that wraps around and substantially surrounds the top and sides of each the semiconducting material ridges along at least a portion of its depth in the gate controlled region.

11. A super-lattice castellated gate heterojunction field effect transistor (SLCFET) comprising:

a plurality of multichannel gate ridges residing over the base structure with each multichannel gate ridge comprising a plurality of heterostructures that each form a portion of a parallel channel of the multichannel gate ridges, the plurality of multichannel gate ridges being spaced apart from one another by gate-controlled non-channel trench openings;

a plurality of multichannel drain ridges residing over the base structure with each multichannel drain ridge comprising a plurality of heterostructures that each form a portion of a parallel channel of the multichannel drain ridges, the plurality of multichannel drain ridges being spaced apart from one another by drain-side non-channel trench openings;

a source region that overlies the base structure and is coupled with a first end of the plurality of multichannel gate ridges;

a drain region that overlies the base structure and is coupled with a first end of the plurality of multichannel drain ridges;

a gate interface formed from the plurality of heterostructures that runs transverse to the plurality of multichannel ridges, is coupled with a second end of the plurality of multichannel gate ridges and a second end of the plurality of multichannel drain ridges, and separates the non-channel trench openings into drain-side non-channel trench openings and gate-controlled non-channel trench openings;

a gate contact that wraps around and substantially surrounds the top and sides of each the plurality of multichannel gate ridges along at least a portion of its depth and fills the gate-controlled non-channel trench openings; and

a doped material disposed in the drain-side non-channel trench openings.

12. The SLCFET of claim 1 , wherein each heterostructure is formed from an AlGaN layer and a GaN layer, wherein the AlGaN layer is doped.

13. The SLCFET of claim 1 , wherein the doped material is boron doped diamond.

14. The SLCFET of claim 1 , wherein the doped material is Mg- or Ca-doped GaN.