Semiconductor device
A semiconductor device according to the present invention includes a semiconductor layer of SiC of a first conductivity type, a plurality of body regions of a second conductivity type formed in the surface portion of the semiconductor layer with each body region forming a unit cell, a source region of the first conductivity type formed in the inner portion of the body region, a gate electrode facing the body region across a gate insulating film, a drain region of the first conductivity type and a collector region of the second conductivity type formed in the rear surface portion of the semiconductor layer such that the drain region and the collector region adjoin each other, and a drift region between the body region and the drain region, wherein the collector region is formed such that the collector region covers a region including at least two unit cells in the x-axis direction along the surface of the semiconductor layer.
1. A semiconductor device comprising:
a wide band gap semiconductor layer of a first conductivity type;
a drift region of the first conductivity type as a portion of the wide band gap semiconductor layer;
a body region of a second conductivity type formed over the drift region as a portion of the wide band gap semiconductor;
a gate trench formed at a surface of the wide band gap semiconductor layer to reach the drift region;
a source region of the first conductivity type formed around the gate trench;
a contact region of the second conductivity type formed in the wide band gap semiconductor layer, the contact region having a certain depth from a rear surface of the wide band gap semiconductor layer toward the surface of the wide band gap semiconductor layer;
a buried impurity region of the second conductivity type formed below the gate trench; and
an insulating layer formed over the gate trench,
wherein the contact region is formed as a grid pattern in a plain view.
2. A semiconductor device according to claim 1 , further comprising a second contact region of the second conductivity type formed adjacent to the source region,
wherein a metal layer is formed to be electrically connected with the source region and the second contact region.
3. A semiconductor device according to claim 2 , wherein a surface of the second contact region is formed lower than a surface of the source region.
4. A semiconductor device according to claim 3 , wherein a bottom edge portion of the gate trench is formed as to include a curvature.
5. A semiconductor device according to claim 4 , wherein a width of the buried impurity region is substantially the same as a width of the gate trench.
6. A semiconductor device according to claim 5 , wherein a gate insulating film is formed along an inner surface of the gate trench.
7. A semiconductor device according to claim 6 , wherein a poly silicon gate electrode is formed in the gate trench to contact with the gate insulating film.
8. A semiconductor device according to claim 7 , wherein the metal layer is formed along a surface of the insulating layer and the surface of the wide band gap semiconductor layer so that a surface of the metal layer is formed to include unevenness in a cross sectional view.
9. A semiconductor device according to claim 8 , wherein the source region is formed in a square shape in a plan view.
10. A semiconductor device according to claim 9 , wherein the buried impurity region is formed to include a curvature in a cross sectional view.
11. A semiconductor device according to claim 10 , wherein the body region is connected to a drain region formed below the body region.
12. A semiconductor device according to claim 11 , wherein the width of the gate trench is substantially constant from a bottom to a top of the gate trench.
13. A semiconductor device according to claim 12 , wherein the metal layer is made mainly of aluminum mainly.
14. A semiconductor device according to claim 13 , wherein the wide band gap semiconductor layer is an SiC layer.
15. A semiconductor device according to claim 1 , further comprising a drain region formed below the body region such that the drain region is exposed from a pattern except for the grid pattern of the contact region.
16. A semiconductor device comprising:
an SiC semiconductor layer of a first conductivity type;
a drift region of the first conductivity type as a portion of the SiC semiconductor layer;
a body region of a second conductivity type formed over the drift region as a portion of the SiC semiconductor;
a gate trench formed at a surface of the SiC semiconductor layer to reach the drift region;
a source region of the first conductivity type formed around the gate trench;
a contact region of the second conductivity type formed in the SiC semiconductor layer, the contact region having a certain depth from a rear surface of the SiC semiconductor layer toward the surface of the SiC semiconductor layer;
a buried impurity region of the second conductivity type formed below the gate trench; and
an insulating layer formed over the gate trench,
wherein the contact region is formed as a grid pattern in a plan view.
17. A semiconductor device according to claim 16 , further comprising a second contact region of the second conductivity type formed adjacent to the source region,
wherein a metal layer is formed to be electrically connected with the source region and the second contact region.
18. A semiconductor device according to claim 17 , wherein a surface of the second contact region is formed lower than a surface of the source region.
19. A semiconductor device according to claim 18 , wherein a bottom edge portion of the gate trench is formed to include a curvature.
20. A semiconductor device according to claim 19 , wherein a width of the buried impurity region is substantially the same as a width of the gate trench.
21. A semiconductor device according to claim 20 , wherein a gate insulating film is formed along an inner surface of the gate trench.
22. A semiconductor device according to claim 21 , wherein a poly silicon gate electrode is formed in the gate trench to contact with the gate insulating film.
23. A semiconductor device according to claim 22 , wherein the metal layer is formed along a surface of the insulating layer and the surface of the SiC semiconductor layer so that a surface of the metal layer is uneven in a cross sectional view.
24. A semiconductor device according to claim 23 , wherein the source region is formed in a square shape in a plan view.
25. A semiconductor device according to claim 24 , wherein the buried impurity region is formed to include a curvature in a cross sectional view.
26. A semiconductor device according to claim 25 , wherein the body region is connected to a drain region formed below the body region.
27. A semiconductor device according to claim 26 , wherein the width of the gate trench is substantially constant from a bottom to a top of the gate trench.
28. A semiconductor device according to claim 27 , wherein the metal layer is made mainly of aluminum mainly.
29. A semiconductor device according to claim 16 , further comprising a drain region formed below the body region such that the drain region is exposed from a pattern except for the grid pattern of the contact region.