Semiconductor device and manufacturing method thereof
In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.
1. A method of manufacturing a negative capacitance structure, the method comprising:
forming a dielectric layer over a substrate;
forming a first metallic layer over the dielectric layer;
after the first metallic layer is formed, performing an annealing operation followed by a cooling operation; and
forming a second metallic layer on the first metallic layer, wherein:
after the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase, and
the first metallic layer includes a single layer of TiN doped with Si, and comprises a (111) oriented crystalline layer.
2. The method of claim 1 , wherein the ferroelectric dielectric layer includes HfO 2 doped with one or more selected from the group consisting of Si, Zr, Al, La, Y, Gd and Sr.
3. The method of claim 1 , wherein the ferroelectric dielectric layer includes a single layer of HfO 2 doped with Zr and comprises a (111) oriented crystalline layer.
4. The method of claim 1 , wherein the annealing operation is performed at a temperature in a range from 700° C. to 1000° C. in an inert gas ambient.
5. The method of claim 1 , wherein the second metallic layer is formed after the cooling operation.
6. The method of claim 1 , wherein the second metallic layer is TaN.
7. The method of claim 1 , wherein the forming a dielectric layer includes alternately forming HfO 2 layers and ZrO 2 layers over a substrate.
8. The method of claim 1 , wherein the dielectric layer as formed is amorphous.
9. The method of claim 1 , wherein the ferroelectric dielectric layer includes HfO 2 doped Ti in an amount of 2 mol % to 5 mol %.
10. A method of manufacturing a negative capacitance structure, the method comprising:
forming a seed dielectric layer over a substrate;
performing a first annealing operation on the seed dielectric layer;
after the first annealing operation, forming a dielectric layer over the seed dielectric layer;
forming a first metallic layer over the dielectric layer; and
after the first metallic layer is formed, performing a second annealing operation followed by a cooling operation, wherein:
after the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase, and the seed dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.
11. The method of claim 10 , wherein the seed dielectric layer is ZrO 2 .
12. The method of claim 10 , wherein the dielectric layer includes HfO 2 containing Zr.
13. The method of claim 10 , wherein the forming a dielectric layer includes alternately forming HfO 2 layers and ZrO 2 layers over a substrate.
14. The method of claim 10 , wherein the second annealing operation is performed at a temperature in a range from 700° C. to 1000° C. in an inert gas ambient.
15. The method of claim 10 , wherein the capping metallic layer includes TiN doped with Si.
16. The method of claim 10 further comprising forming a second metallic layer over the dielectric layer.
17. The method of claim 16 , wherein the second layer is formed after the cooling operation.
18. The method of claim 10 , further comprising forming an interfacial oxide layer over the substrate before the seed dielectric layer is formed.
19. A negative capacitance field effect transistor (NC-FET), comprising:
a channel layer made of a semiconductor;
a ferroelectric dielectric layer disposed over the channel layer;
a metallic film comprising a (111) oriented crystalline layer; and
a gate electrode layer disposed over the ferroelectric dielectric layer,
wherein the ferroelectric dielectric layer includes a single layer of HfZrO 2 comprising a (111) oriented orthorhombic crystal.
20. The NC-FET of claim 19 , further comprising a silicon oxide layer having a thickness in a range from 0.5 nm to 1.5 nm between the channel layer and the ferroelectric dielectric layer.