Gate-all-around transistor based non-volatile memory devices
A semiconductor device including a gate-all-around based non-volatile memory device includes isolated channels including tunnel dielectric material disposed around gate-all-around field effect transistor (GAA FET) channels, at least one floating gate including a first gate material encapsulating the isolated channels, and at least one control gate including a second gate material encapsulating the isolated channels.
1. A semiconductor device including a gate-all-around based non-volatile memory device, comprising:
isolated channels including tunnel dielectric material disposed around gate-all-around field effect transistor (GAA FET) channels;
at least one floating gate including a first gate material encapsulating the isolated channels; and
at least one control gate including a second gate material encapsulating the isolated channels.
2. The device of claim 1 , wherein the floating gate is positioned between a first control gate and a second control gate.
3. The device of claim 1 , wherein the first gate material and second gate material each include polysilicon.
4. The device of claim 1 , further comprising inter-poly dielectric (IPD) material disposed between the floating gate and the at least one control gate.
5. The device of claim 1 , wherein the tunnel dielectric material includes silicon dioxide (SiO 2 ).
6. The device of claim 1 , further comprising at least one gate contact.
7. The device of claim 1 , wherein the GAA FET channels include a stack of nanosheets.
8. A semiconductor device including a gate-all-around based non-volatile memory device, comprising:
isolated channels including tunnel dielectric material disposed around gate-all-around field effect transistor (GAA FET) channels;
a floating gate including a first gate material encapsulating the isolated channels; and
dual control gates including a second gate material encapsulating the isolated channels.
9. The device of claim 8 , wherein the floating gate is positioned between the dual control gates.
10. The device of claim 8 , wherein the first gate material and second gate material each include polysilicon.
11. The device of claim 8 , further comprising inter-poly dielectric (IPD) material disposed between the floating gate and the dual control gates.
12. The device of claim 8 , wherein the tunnel dielectric material includes silicon dioxide (SiO 2 ).
13. The device of claim 8 , further comprising at least one gate contact.
14. A semiconductor device including a gate-all-around field-effect transistor (GAA FET) based non-volatile memory device, comprising:
isolated channels including tunnel dielectric material disposed around gate-all-around field effect transistor (GAA FET) channels;
at least one floating gate including at least one portion of first gate material encapsulating at least one of the isolated channels;
a dielectric layer conformally formed around the at least one portion of first gate material; and
a control gate including a second gate material encapsulating the dielectric layer.
15. The device of claim 14 , wherein the at least one floating gate is merged within the control gate.
16. The device of claim 14 , wherein the at least one floating gate includes a plurality of floating gates.
17. The device of claim 14 , wherein the first gate material and second gate material each include polysilicon.
18. The device of claim 14 , further comprising inter-poly dielectric (IPD) material disposed between the floating gate and the control gate.
19. The device of claim 14 , wherein the tunnel dielectric material includes silicon dioxide (SiO 2 ).
20. The device of claim 14 , further comprising at least one gate contact.