Vertical josephson junction superconducting device
Techniques for a vertical Josephson junction superconducting device are provided. In one embodiment, a chip surface base device structure is provided that comprises a substrate comprising crystalline silicon that is coupled with a first superconducting layer, wherein the first superconducting layer is coupled with a second substrate comprising crystalline silicon. In one implementation, the chip surface base device structure also comprises a vertical Josephson junction located in an etched region of the substrate, the vertical Josephson junction comprising a first superconducting layer, a tunnel barrier layer, and a top superconducting layer.
1. A chip surface base device structure, comprising:
a substrate that is physically coupled with a first superconducting layer; and
a vertical Josephson junction located in an etched region of the substrate, the vertical Josephson junction comprising the first superconducting layer, a tunnel barrier layer, and a top superconducting layer, wherein the vertical Josephson junction comprises a third superconducting layer that is deposited above the tunnel barrier layer.
2. The chip surface base device structure of claim 1 , further comprising:
a via in the etched region of the substrate.
3. The chip surface base device structure of claim 1 , wherein the tunnel barrier layer is located on at least one of the first superconducting layer, or a second superconducting layer that is physically coupled with the first superconducting layer.
4. The chip surface base device structure of claim 1 , wherein the first superconducting layer comprises a first electrode of the vertical Josephson junction, and the top superconducting layer located on an opposite side of the tunnel barrier layer from the first superconducting layer comprises a top electrode of the vertical Josephson junction.
5. The chip surface base device structure of claim 1 , wherein the vertical Josephson junction comprises a first electrode comprising the first superconducting layer or a second superconducting layer, and a second electrode comprising the top superconducting layer.
6. The chip surface base device structure of claim 1 , wherein the third superconducting layer is deposited above the first superconducting layer and the tunnel barrier layer or above a second superconducting layer and the tunnel barrier layer.
7. A method, comprising:
physically coupling a substrate with a first superconducting layer;
etching the substrate;
forming a vertical Josephson junction in the etching of the substrate, the vertical Josephson junction comprising the first superconducting layer, a tunnel barrier layer, and a top superconducting layer, wherein the forming the vertical Josephson junction comprises:
depositing a second superconducting layer between the first superconducting layer and the tunnel barrier layer, wherein portions of the second superconducting layer are separated by a gap.
8. The method of claim 7 , wherein the forming the vertical Josephson junction further comprises:
depositing the tunnel barrier layer by performing the process within a group consisting of sputtering, evaporating, atomic layer deposition, growth, chemical modification, and oxidation.
9. The method of claim 7 , wherein a height of the second superconducting layer is shorter than a second height of the etching of the substrate, wherein the second height comprises an initial height of the etching of the substrate upon forming the etching.
10. The method of claim 7 , wherein the forming the vertical Josephson junction further comprises:
depositing a third superconducting layer on the tunnel barrier layer.
11. The method of claim 10 , wherein the second superconducting layer and the third superconducting layer are of a different type.
12. The method of claim 10 , wherein the forming the vertical Josephson junction further comprises:
performing chemical-mechanical planarization to remove a portion of the third superconducting layer.
13. The method of claim 7 , further comprising:
forming a via employing a mask and a reactive ion etch; and
forming the vertical Josephson junction within the via.
14. A chip surface base device structure, comprising:
a substrate adjacent to a first superconducting layer; and
a vertical Josephson junction located in an etched region of the substrate, the vertical Josephson junction comprising the first superconducting layer, a tunnel barrier layer, and a top superconducting layer, wherein the vertical Josephson junction comprises a third superconducting layer that is deposited above the tunnel barrier layer.
15. The chip surface base device structure of claim 14 , wherein the tunnel barrier layer is formed on the first superconducting layer.
16. The chip surface base device structure of claim 14 , wherein the vertical Josephson junction comprises a second superconducting layer that is located above the first superconducting layer and below the tunnel barrier layer.
17. The chip surface base device structure of claim 16 , wherein the first superconducting layer and the second superconducting layer comprise an electrode of the vertical Josephson junction.
18. The chip surface base device structure of claim 14 , wherein the vertical Josephson junction comprises a first electrode comprising the first superconducting layer or a second superconducting layer, and a second electrode comprising the top superconducting layer.
19. The chip surface base device structure of claim 14 , wherein the vertical Josephson junction comprises a first electrode comprising the first superconducting layer or a second superconducting layer, and a second electrode comprising the top superconducting layer.
20. The chip surface base device structure of claim 14 , wherein the third superconducting layer is deposited above the first superconducting layer and the tunnel barrier layer or above a second superconducting layer and the tunnel barrier layer.