GaN FET gate driver for self-oscillating converters
A power converter in which two power FETs are provided in a full bridge arrangement with two diodes for supplying a rectified voltage to a load. The gates of the power FETs receive alternating and opposite voltage waveforms such that the power FETs conduct oppositely to each other. A turn-off FET is connected to the gate of each power FET to prevent spurious turn on of the power FET during periods in which the opposite power FET is turned on. A voltage sense FET is also connected to the gate of each power FET to limit the gate voltage of the power FET. The voltage sense FETs are each synchronously modulated with the corresponding power FET to limit the gate to source voltage of the voltage sense FET when the corresponding turn-off FET is on and the corresponding power FET is off.
1. A power converter circuit comprising:
a power converter comprising first and second power FETs having respective gates receiving respective alternating and opposite voltage waveforms such that the first and second power FETs conduct oppositely to each other;
first and second turn-off FETs having: (i) respective drains connected to the gates of the first and second power FETs; (ii) respective sources connected to ground; and (iii) respective gates connected to the gates of opposite ones of the first and second power FETs, to prevent spurious turn on of the first and second power FETs during periods in which the opposite first and second power FETs is turned on; and
first and second voltage sense FETs having respective sources connected to the respective drains of the first and second turn-off FETs and to the respective gates of the first and second power FETs to limit the voltage applied to the respective gates of the first and second power FETs, the first and second voltage sense FETs having respective gates synchronously modulated with the first and second power FETs to limit the gate to source voltage of the voltage sense FETs when the corresponding turn-off FET is on and the corresponding power FET is off.
2. The power converter circuit of claim 1 , wherein the first and second power FETs are GaN FETs.
3. The power converter circuit of claim 1 , wherein the first and second turn-off FETs are GaN FETs.
4. The power converter circuit of claim 1 , wherein the first and second voltage sense FETs are GaN FETs.
5. The power converter circuit of claim 1 , wherein the power converter is implemented in a current-mode class D configuration.
6. The power converter circuit of claim 1 , wherein the power converter is implemented in a class E configuration.
7. The power converter circuit of claim 1 , further comprising first and second current mirror circuits connected to the gates of the first and second current sense FETs for synchronously modulating each of the first and second voltage sense FETs with the corresponding power FET to limit the gate to source voltage of the voltage sense FET when the corresponding turn-off FET is on and the corresponding power FET is off.
8. The power converter circuit of claim 1 , further comprising first and second voltage clamps coupled to the gates of the first and second power FETs, respectively.
9. The power converter circuit of claim 1 , further comprising first and second gate resistors coupled to the gates of the first and second power FETs, respectively, to maintain the respective first and second power FETs at zero volts in an off state.