Low power integrated clock gating system and method
According to one general aspect, an apparatus may include a latch circuit configured to, depending in part upon a state or at least one enable signal, pass a clock signal to an output signal. The latch circuit may include an input stage controlled by the clock signal and the enable signal(s). The latch may include an output stage configured to produce the output signal. The input and output stages may share a common transistor controlled by the clock signal.
1. An apparatus comprising:
a latch circuit configured to, depending in part upon a state of at least one enable signal, pass a clock signal to an output signal, wherein the latch circuit comprises:
a feedback circuit having an inverter, wherein the inverter is powered by the output signal,
an input stage controlled by the clock signal and the at least one enable signal, and
an output stage configured to produce the output signal, and
wherein the input and output stages share a common transistor controlled by the clock signal.
2. The apparatus of claim 1 , wherein the output stage includes the common transistor and a second transistor, both controlled by the clock signal and coupled in series so as to reduce leakage current from the output stage.
3. The apparatus of claim 1 , wherein an output of the inverter is configured to be of a high voltage only when the clock signal and the at least one enable signal are both substantially at the high voltage.
4. The apparatus of claim 1 , wherein the inverter is configured to power down based, at least in part, upon the at least one enable signal.
5. The apparatus of claim 1 , wherein the output stage comprises a pre-charge circuit controlled by the clock signal.
6. The apparatus of claim 1 , wherein the latch circuit is configured to have no full transitions from a high to a low power rail when the at least one enable signal indicate that the output signal should be disabled.
7. The apparatus of claim 1 , wherein an output of the inverter is configured to be of a first voltage only when the clock signal and the at least one enable signal are both substantially at the first voltage.
8. A system comprising:
a clock generator circuit configured to generate a first clock signal;
a clock gater circuit configured to receive the first clock signal, and at least one enable signal as input, and generate a second clock signal; and
a logic circuit configured to perform a logic function synchronized, at least in part by the second clock signal; and
wherein the clock gater circuit comprises:
a feedback circuit having an inverter, wherein the inverter is powered by the second clock signal,
an input stage controlled by the first clock signal and the at least one enable signal, and
an output stage configured to produce the second clock signal, and
wherein the input and output stages share a common transistor controlled by the first clock signal.
9. The system of claim 8 , wherein the clock gater circuit is configured to have no full transitions from a high to a low power rail when the at least one enable signal indicate that the second clock signal should be disabled.