IP Library › Granted Patent US 10,784,883
Granted Patent B1
US 10,784,883 · App. 16/664,554 · Granted Sep 22, 2020

Noise shaping analog-to-digital converter

Inventors: Prateek Tripathi (Cambridge, GB); Behzad Sheikholeslami (Cambridge, GB); Marceline Kelly Tchambake Yapti (Waterbeach, GB)
Assignee: QUALCOMM Incorporated
H03M1/442H03M1/06H03M1/124H03M1/66H03M1/00H03M1/001H03M1/747H03M1/804
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Quick Facts
Patent No.
US 10,784,883
App. No.
16/664,554
Granted
Sep 22, 2020
Kind
B1
Abstract

In certain aspects, an analog-to-digital converter includes a first capacitive digital-to-analog converter (DAC), a second capacitive DAC, and a comparator including a first input, a second input, and an output. The analog-to-digital converter also includes a switch circuit including a first input coupled to the first capacitive DAC, a second input coupled to the second capacitive DAC, a first output coupled to the first input of the comparator, and a second output coupled to the second input of the comparator. The analog-to-digital converter further includes a first switch coupled between the output of the comparator and the first input of the comparator, and a successive approximation register (SAR) coupled to the output of the comparator, the first capacitive DAC, and the second capacitive DAC.

Claims (73)

1. An analog-to-digital converter, comprising:

a first capacitive digital-to-analog converter (DAC);

a second capacitive DAC;

a comparator including a first input, a second input, and an output;

a switch circuit including a first input coupled to the first capacitive DAC, a second input coupled to the second capacitive DAC, a first output coupled to the first input of the comparator, and a second output coupled to the second input of the comparator;

a first switch coupled between the output of the comparator and the first input of the comparator; and

a successive approximation register (SAR) coupled to the output of the comparator, the first capacitive DAC, and the second capacitive DAC.

2. The analog-to-digital converter of claim 1 , wherein the comparator comprises an amplifier including an inverting input coupled to the first input of the comparator, a non-inverting input coupled to the second input of the comparator, and an output coupled to the output of the comparator.

3. The analog-to-digital converter of claim 1 , further comprising a second switch coupled between the second input of the comparator and a compare voltage.

4. The analog-to-digital converter of claim 3 , further comprising a switch controller, wherein the switch controller is configured to:

close the first switch and open the second switch to operate the comparator in a feedback mode; and

open the first switch and close the second switch to operate the comparator in a compare mode.

5. The analog-to-digital converter of claim 3 , wherein the compare voltage comprises a ground.

6. The analog-to-digital converter of claim 1 , wherein:

during a sampling phase of a first conversion cycle, the first capacitive DAC is configured to sample an analog input voltage;

during a conversion phase of the first conversion cycle, the SAR is configured to:

output a first digital signal to the first capacitive DAC; and

resolve N bits of the first digital signal based on a compare signal from the output of the comparator.

7. The analog-to-digital converter of claim 6 , wherein:

during a sampling phase of a second conversion cycle, the second capacitive DAC is configured to sample the analog input voltage;

during a conversion phase of the second conversion cycle, the SAR is configured to:

output a second digital signal to the second capacitive DAC; and

resolve N bits of the second digital signal based on the compare signal from the output of the comparator.

8. The analog-to-digital converter of claim 7 , further comprising a switch controller, wherein the switch controller is configured to close the first switch during the sampling phase of the second conversion cycle.

9. The analog-to-digital converter of claim 8 , wherein the switch controller is configured to open the first switch during the conversion phase of the second conversion cycle.

10. The analog-to-digital converter of claim 7 , wherein:

the switch circuit is configured to:

selectively couple the first capacitive DAC to the first input of the comparator or the second input of the comparator; and

selectively couple the second capacitive DAC to the first input of the comparator or the second input of the comparator; and

the analog-to-digital converter further comprises a switch controller, wherein the switch controller is configured to:

instruct the switch circuit to couple the first capacitive DAC to the second input of the comparator during the sampling phase of the second conversion cycle; and

instruct the switch circuit to couple the second capacitive DAC to the first input of the comparator during the sampling phase of the second conversion cycle.

11. The analog-to-digital converter of claim 10 , wherein the switch controller is configured to close the first switch during the sampling phase of the second conversion cycle.

12. The analog-to-digital converter of claim 11 , wherein the switch controller is configured to open the first switch during the conversion phase of the second conversion cycle.

13. The analog-to-digital converter of claim 12 , further comprising a second switch coupled between the second input of the comparator and a compare voltage, wherein the switch controller is configured to:

open the second switch during the sampling phase of the second conversion cycle; and

close the second switch during the conversion phase of the second conversion cycle.

14. The analog-to-digital converter of claim 1 , wherein:

the first capacitive DAC comprises:

a first capacitor array; and

a first switch network coupled to the first capacitor array; and

the second capacitive DAC comprises:

a second capacitor array; and

a second switch network coupled to the second capacitor array.

15. The analog-to-digital converter of claim 14 , wherein the first capacitor array comprises a first set of binary-weighted capacitors, and the second capacitor array comprises a second set of binary-weighted capacitors.

16. A method for noise shaping in an analog-to-digital converter,

wherein the analog-to-digital converter includes a first capacitive digital-to-analog converter (DAC), a second DAC, and a comparator, the method comprising:

coupling an output of the first capacitive DAC to a first input of the comparator;

coupling an output of the second capacitive DAC to a second input of the comparator;

coupling an output of the comparator to the first input of the comparator;

after the output of the comparator is coupled to the first input of the comparator, decoupling the output of the comparator from the first input of the comparator; and

coupling the second input of the comparator to a compare voltage.

17. The method of claim 16 , further comprising sampling an analog input voltage using the first capacitive DAC.

18. The method of claim 16 , wherein the compare voltage comprises a ground.

19. The method of claim 16 , wherein, after the output of the comparator is decoupled from the first input of the comparator, the method further comprises:

inputting a digital signal to the first capacitive DAC; and

resolving N bits of the digital signal based on a compare signal from the output of the comparator.

20. The method of claim 19 , wherein, after the N bits of the digital signal are resolved, the method further comprises:

decoupling the second input of the comparator from the compare voltage;

coupling the output of the first capacitive DAC to the second input of the comparator;

coupling the output of the second capacitive DAC to the first input of the comparator; and

coupling the output of the comparator to the first input of the comparator.

21. The method of claim 16 , wherein the comparator comprises an amplifier including an inverting input coupled to the first input of the comparator, a non-inverting input coupled to the second input of the comparator, and an output coupled to the output of the comparator.

22. An apparatus for noise shaping in an analog-to-digital converter, wherein the analog-to-digital converter includes a first capacitive digital-to-analog converter (DAC), a second DAC, and a comparator, the apparatus comprising:

means for coupling an output of the first capacitive DAC to a first input of the comparator;

means for coupling an output of the second capacitive DAC to a second input of the comparator;

means for coupling an output of the comparator to the first input of the comparator;

means for decoupling the output of the comparator from the first input of the comparator after the output of the comparator is coupled to the first input of the comparator; and

means for coupling the second input of the comparator to a compare voltage.

23. The apparatus of claim 22 , wherein the compare voltage comprises a ground.

24. The apparatus of claim 22 , wherein the apparatus further comprises:

means for inputting a digital signal to the first capacitive DAC after the output of the comparator is decoupled from the first input of the comparator; and

means for resolving N bits of the digital signal based on a compare signal from the output of the comparator.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2019
From: TRIPATHI, PRATEEK; SHEIKHOLESLAMI, BEHZAD; TCHAMBAKE YAPTI, MARCELINE KELLY
To: QUALCOMM INCORPORATED
Reel/Frame 051339/0038 →
Cited By (2)
US 12,512,845 US 12,574,040