High-order noise-shaping successive approximation register (SAR) analog-to-digital converter and method thereof
A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) comprises: a plurality of switch capacitor arrays, used to sample an analog input signal; a noise shaping circuit including a fourth-order CIFF (Cascade of Integrators with Feed-Forward) loop filter having two second-order cascaded CIFF loop filters, in the fourth-order CIFF loop filter, a first-order extraction capacitor and a second-order extraction capacitor sharing a first amplifier, and a third-order extraction capacitor and a fourth-order extraction capacitor sharing a second amplifier; a comparator for comparing a plurality of output signals from the noise shaping circuit to produce a plurality of comparison results; and a logic circuit for generating a digital output signal and controlling the switch capacitor arrays based on comparison results from the comparator.
1 . A successive approximation register analog-to-digital converter comprising:
a plurality of switch capacitor arrays for acquiring an analog input signal;
a noise shaping circuit coupled to said switch capacitor arrays, said noise shaping circuit comprising a multi-order Cascade of Integrators with Feed-Forward (CIFF) circuit having a plurality of amplifiers, a plurality of integration capacitors, and a plurality of extraction capacitors;
a comparator coupled to said noise shaping circuit, said comparator for comparing a plurality of output signals of said noise shaping circuit to generate a plurality of comparison results; and
a logic circuit coupled to said switch capacitor arrays and said comparator, said logic circuit generating a digital output signal and controlling said switch capacitor arrays based on said comparison results.
2 . The successive approximation register analog-to-digital converter according to claim 1 , wherein said multi-order CIFF circuit is a fourth-order CIFF circuit having two cascaded second-order CIFF circuits.
3 . The successive approximation register analog-to-digital converter according to claim 1 , wherein:
a first switch capacitor array of said switch capacitor arrays comprises a plurality of first capacitors, a plurality of first switches, and a first multiplexer group;
a second switch capacitor array of said switch capacitor arrays comprises a plurality of second capacitors, a plurality of second switches, and a second multiplexer group;
said first capacitors and said second capacitors are coupled in series to said first switches and said second switches, respectively;
said first switches and said second switches selectively input the analog input signal or a plurality of output signals of said first and second multiplexer groups into said first and second capacitors, respectively; and
each of said first and second multiplexer groups comprises a plurality of multiplexers, said first and second multiplexer groups selecting from a first reference voltage, a second reference voltage, and a common-mode voltage to output to said first and second switches.
4 . The successive approximation register analog-to-digital converter according to claim 3 , wherein:
said noise shaping circuit comprises a plurality of first integration capacitors, a plurality of second integration capacitors, a plurality of first extraction capacitors, a plurality of second extraction capacitors, and first and second amplifiers;
said first integration capacitors are in series;
said second integration capacitors are in series; and
said first extraction capacitors are selectively coupled between a positive output terminal and a negative output terminal of said first amplifier, and said second extraction capacitors are selectively coupled between a positive output terminal and a negative output terminal of said second amplifier.
5 . The successive approximation register analog-to-digital converter according to claim 4 , wherein, in a sampling phase:
the analog input signal is sampled to a plurality of lower plates of said first and second switch capacitor arrays; and
a portion of said first integration capacitors and a portion of said second integration capacitors are reset.
6 . The successive approximation register analog-to-digital converter according to claim 5 , wherein,
during a conversion phase, the comparator performs a plurality of comparison processes;
in a sharing phase, said first and second extraction capacitors are coupled in parallel to said first and second integration capacitors, and charge redistribution is performed, with the conversion phase and the sharing phase occurring simultaneously;
in the comparison processes, a plurality of output signals of said first and second switch capacitor arrays enter said noise shaping circuit and are added to said first and second integration capacitors; and
the comparator compares a first sum and a second sum, where the first sum is obtained by adding a first analog input signal of the analog input signal to a plurality of first integration voltages of the first integration capacitors, and the second sum is obtained by adding a second analog input signal of the analog input signal to a plurality of second integration voltages of the second integration capacitors.
7 . The successive approximation register analog-to-digital converter according to claim 6 , wherein, in an extraction phase:
a voltage of a first part of said first integration capacitors and a voltage of a first part of said second integration capacitors are amplified by said first amplifier and stored on said first extraction capacitors; and
a voltage of a second part of said first integration capacitors and a voltage of a second part of said second integration capacitors are amplified by said second amplifier and stored on said second extraction capacitors.
8 . A successive approximation register analog-to-digital converter comprising:
a plurality of switch capacitor arrays for acquiring an analog input signal;
a noise shaping circuit comprising a fourth-order CIFF loop filter having two second-order cascaded CIFF loop filters, wherein in the fourth-order CIFF loop filter, a first order extraction capacitor and a second order extraction capacitor share a first amplifier, and a third order extraction capacitor and a fourth order extraction capacitor share a second amplifier;
a comparator, two input terminals of the comparator respectively coupled to a plurality of integration capacitors of the fourth-order CIFF loop filter, the comparator comparing a plurality of output signals of the noise shaping circuit to generate a plurality of comparison results, the noise shaping circuit being positioned after said switch capacitor arrays and before said comparator; and
a logic circuit, an output terminal of the comparator coupled to an input terminal of the logic circuit, three output terminals of the logic circuit respectively coupled to said switch capacitor arrays for generating a digital output signal, and the logic circuit generating the digital output signal based on the comparison results of said comparator to control said switch capacitor arrays.
9 . The successive approximation register analog-to-digital converter according to claim 8 , wherein, in a sampling phase:
the analog input signal is sampled to a plurality of lower plates of said switch capacitor arrays; and
a portion of said plurality of integration capacitors of the fourth-order CIFF loop filter are reset.
10 . The successive approximation register analog-to-digital converter according to claim 9 , wherein,
in a conversion phase, the comparator performs comparisons;
in a sharing phase, said first order extraction capacitor, said second order extraction capacitor, said third order extraction capacitor, and said fourth order extraction capacitor are coupled in parallel to said plurality of integration capacitors of the fourth-order CIFF loop filter for performing charge sharing and redistribution, wherein the conversion phase and the sharing phase occurring simultaneously;
the analog input signal sampled by the plurality of lower plates of said switch capacitor arrays is pushed to a plurality of upper plates of said switch capacitor arrays;
in the conversion phase, the comparator performs comparisons, and the logic circuit controls said switch capacitor arrays;
after the conversion phase ends, a plurality of voltages of the plurality of upper plates of said switch capacitor arrays is a residual voltage after the conversion phase;
a noise transfer function of the fourth-order CIFF loop filter is determined by a capacitance ratio of said plurality of integration capacitors and amplification ratios of the first and second amplifiers; and
when a comparison number of the comparator reaches a bit number of the successive approximation register analog-to-digital converter, the conversion phase ends, and the logic circuit outputs the digital output signal.
11 . The successive approximation register analog-to-digital converter according to claim 10 , wherein, in an extraction phase:
the noise shaping circuit uses said first and second amplifiers and said plurality of integration capacitors to amplify a plurality of integration voltages of said plurality of integration capacitors by a gain factor, and extracts a processing result to said first order extraction capacitor, said second order extraction capacitor, said third order extraction capacitor, and said fourth order extraction capacitor.
12 . A method for successive approximation register analog-to-digital conversion, comprising:
in a sampling phase, sampling an analog input signal to a plurality of lower plates of a first and a second switch capacitor arrays, and resetting a portion of a plurality of first integration capacitors and a portion of a plurality of second integration capacitors of a fourth-order CIFF loop filter;
in a conversion phase, performing a plurality of comparison processes by a comparator;
in a sharing phase, coupling a plurality of first extraction capacitors and a plurality of second extraction capacitors of the fourth-order CIFF loop filter in parallel to the first integration capacitors and the second integration capacitors for charge redistribution, wherein the conversion phase and the sharing phase occurring simultaneously;
in the comparison processes, adding a plurality of output signals of the first and second switch capacitor arrays to the first and the second integration capacitors; comparing a plurality of summing having a plurality of integration voltages of the first and the second integration capacitors and a plurality of input signals by the comparator; and
in an extraction phase, amplifying the integration voltages of the plurality of first integration capacitors and the plurality of second integration capacitors using a first and a second amplifier, and storing on the first and the second extraction capacitors.