Noise-shaping successive approximation register (SAR) analog-to-digital converter

1. An analog-to-digital converter (ADC), comprising:

a comparator having a first input, a second input, and an output;

a digital-to-analog converter (DAC) coupled to the first input of the comparator;

a switching circuit;

a first capacitor coupled between the first input of the comparator and the switching circuit;

a second capacitor coupled between the first input of the comparator and the switching circuit;

an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to the switching circuit;

a first switch coupled between the output of the amplifying circuit and the DAC; and

a successive approximation register (SAR) having an input and an output, wherein the input of the SAR is coupled to the output of the comparator, and the output of the SAR is coupled to the DAC.

2. The ADC of claim 1 , wherein the second input of the comparator is coupled to a common mode voltage or a ground.

3. The ADC of claim 1 , wherein the DAC comprises a capacitive DAC.

4. The ADC of claim 1 , wherein the amplifying circuit comprises:

an amplifier having a first input, a second input, and an output, wherein the first input of the amplifier is coupled to the input of the amplifying circuit, and the output of the amplifier is coupled to the output of the amplifying circuit.

5. The ADC of claim 4 , wherein the second input of the amplifier is coupled to a ground.

6. The ADC of claim 4 , further comprising a controller configured to:

during a sampling phase, turn on the first switch; and

during a conversion phase, turn off the first switch.

7. The ADC of claim 6 , wherein, during the conversion phase, the SAR is configured to:

output a digital signal to the DAC; and

resolve N bits of the digital signal based on a compare signal from the output of the comparator.

8. The ADC of claim 4 , wherein the amplifying circuit further comprises a second switch coupled between the output of the amplifier and the first input of the amplifier.

9. The ADC of claim 8 , wherein the amplifying circuit further comprises a third switch coupled between the first input of the amplifier and a ground.

10. The ADC of claim 9 , further comprising a controller configured to:

during a sampling phase, turn on the first switch, turn off the second switch, and turn off the third switch; and

during a conversion phase, turn off the first switch, turn on the second switch, and turn on the third switch.

11. The ADC of claim 10 , wherein, during the conversion phase, the SAR is configured to:

output a digital signal to the DAC; and

resolve N bits of the digital signal based on a compare signal from the output of the comparator.

12. The ADC of claim 9 , wherein the amplifying circuit further comprises a fourth switch coupled between the output of the amplifier and a common mode voltage.

13. The ADC of claim 1 , wherein the switching circuit comprises:

a second switch coupled between a terminal of the first capacitor and an input of the ADC;

a third switch coupled between a terminal of the second capacitor and the input of the ADC;

a fourth switch coupled between the terminal of the first capacitor and the input of the amplifying circuit; and

a fifth switch coupled between the terminal of the second capacitor and the input of the amplifying circuit.

14. The ADC of claim 13 , further comprising a controller configured to:

during a first sampling phase, turn on the second switch, turn off the third switch, turn off the fourth switch, and turn on the fifth switch; and

during a second sampling phase, turn off the first switch, turn on the third switch, turn on the fourth switch, and turn off the fifth switch.

15. The ADC of claim 13 , wherein the switching circuit further comprises:

a sixth switch coupled between the terminal of the first capacitor and a ground; and

a seventh switch coupled between the terminal of the second capacitor and the ground.

16. The ADC of claim 15 , further comprising a controller configured to:

during a first sampling phase, turn on the second switch, turn off the third switch, turn off the fourth switch, turn on the fifth switch, turn off the sixth switch, and turn off the seventh switch;

during a first conversion phase, turn off the second switch, turn off the third switch, turn off the fourth switch, turn off the fifth switch, turn on the sixth switch, and turn off the seventh switch;

during a second sampling phase, turn off the second switch, turn on the third switch, turn on the fourth switch, turn off the fifth switch, turn off the sixth switch, and turn off the seventh switch; and

during a second conversion phase, turn off the second switch, turn off the third switch, turn off the fourth switch, turn off the fifth switch, turn off the sixth switch, and turn on the seventh switch.

17. The ADC of claim 16 , wherein, during each of the first conversion phase and the second the conversion phase, the SAR is configured to:

output a digital signal to the DAC; and

resolve N bits of the digital signal based on a compare signal from the output of the comparator.

18. The ADC of claim 16 , wherein, during each of the first sampling phase and the second the sampling phase, the controller is configured to turn on the first switch.

19. The ADC of claim 18 , wherein, during each of the first conversion phase and the second the conversion phase, the controller is configured to turn off the first switch.

20. The ADC of claim 1 , wherein the switching circuit is configured to:

during a first sampling phase, couple a terminal of the first capacitor to an input of the ADC and couple a terminal of the second capacitor to the input of the amplifying circuit; and

during a second sampling phase, couple the terminal of the second capacitor to the input of the ADC and couple the terminal of the first capacitor to the input of the amplifying circuit.

21. The ADC of claim 20 , wherein the switching circuit is further configured to:

during a first conversion phase, couple the terminal of the first capacitor to a ground; and

during a second conversion phase, couple the terminal of the second capacitor to the ground.

22. The ADC of claim 21 , wherein the switching circuit is further configured to:

during the first conversion phase, float the terminal of the second capacitor; and

during the second conversion phase, float the terminal of the first capacitor.

23. The ADC of claim 21 , wherein, during each of the first conversion phase and the second the conversion phase, the SAR is configured to:

output a digital signal to the DAC; and

resolve N bits of the digital signal based on a compare signal from the output of the comparator.

24. A system, comprising:

an analog-to-digital converter (ADC), comprising:

a comparator having a first input, a second input, and an output;

a digital-to-analog converter (DAC) coupled to an input of the ADC and the first input of the comparator;

a switching circuit coupled to the input of the ADC;

a first capacitor coupled between the first input of the comparator and the switching circuit;

a second capacitor coupled between the first input of the comparator and the switching circuit;

an amplifying circuit having an input and an output, wherein the input of the amplifying circuit is coupled to the switching circuit;

a first switch coupled between the output of the amplifying circuit and the DAC; and

a successive approximation register (SAR) having an input, a first output, and a second output, wherein the input of the SAR is coupled to the output of the comparator, the first output of the SAR is coupled to the DAC, and the second output is coupled to an output of the ADC;

a receiver coupled to the input of the ADC; and

a processor coupled to the output of the ADC.

25. A method for noise shaping in an analog-to-digital converter (ADC), wherein the ADC includes a digital-to-analog converter (DAC) having an output, a comparator having a first input coupled to the output of the DAC and a second input coupled to a common mode voltage or a ground, a first capacitor, and an amplifying circuit, the method comprising:

during a first sampling phase,

coupling the first capacitor between the output of the DAC and an input of the ADC;

during a first conversion phase,

coupling the first capacitor between the output of the DAC and a ground; and

during a second sampling phase,

coupling the first capacitor between the output of the DAC and an input of the amplifying circuit; and

coupling an output of the amplifying circuit to the output of the DAC.

26. The method of claim 25 , wherein the ADC also includes a second capacitor, and the method further comprises:

during the first sampling phase,

coupling the second capacitor between the output of the DAC and the input of the amplifying circuit; and

coupling the output of the amplifying circuit to the output of the DAC;

during the second sampling phase,

coupling the second capacitor between the output of the DAC and the input of the ADC; and

during a second conversion phase,

coupling the second capacitor between the output of the DAC and the ground.

27. The method of claim 26 , further comprising:

during each of the first conversion phase and the second conversion phase,

outputting a digital signal to the DAC; and

resolving N bits of the digital signal based on a compare signal from an output of the comparator.