Graphics hardware driven pause for quality of service adjustment

1. A non-transitory program storage device, readable by one or more processors and comprising instructions stored thereon to cause the one or more processors to:

generate a priority list for a plurality of data masters for graphics processor based on a comparison between a current utilizations for the data masters and a target utilizations for the data masters;

assign, based on the priority list, a first data master of the plurality of data masters as a designated data master, wherein the designated data master has a higher priority to submit work to the graphics processor compared to a second data master of the plurality of data masters;

determine a stall counter value for the designated data master, wherein the stall counter value is indicative of a number of time periods the designated data master has work to submit to the graphics processor, but is unable to submit the work; and

generate a notification to pause work for the second data master based on the stall counter value.

2. The non-transitory program storage device of claim 1 , where the instructions further cause the one or more processors to:

send priority information indicating that the designated data master has a higher priority to a cluster;

receive, based on the priority information, a cluster stall counter value indicative of a number of time periods the cluster is unable to process the work for the designated data master; and

determine the stall counter value based on the cluster stall counter value.

3. The non-transitory program storage device of claim 2 , wherein the instructions to determine the stall counter value comprises instructions that cause the one or more processors to:

receive a second cluster stall counter value from a second cluster;

determine a maximum stall counter value based on the second cluster stall counter value and the cluster stall counter value; and

set the maximum stall counter value as the stall counter value.

4. The non-transitory program storage device of claim 2 , wherein the instructions to determine the stall counter value comprises instructions that cause the one or more processors to:

receive a second cluster stall counter value from a second hardware resource cluster; and

averaging the second cluster stall counter value with the cluster stall counter value to generate the stall counter value.

5. The non-transitory program storage device of claim 1 , wherein the number of time periods represents a number of graphics processor clock cycles during which the first data master has the work to submit the graphics processor, but is unable to submit the work.

6. The non-transitory program storage device of claim 1 , where the instructions further cause the one or more processors to:

update the priority list after generating the notification to pause the second data master, wherein the updated priority list indicates that a third data master of the plurality of data masters has been assigned a highest priority to submit work to the graphics processor amongst the plurality of data masters;

designate, based on the updated priority list, the third data master of the plurality of data masters with a higher priority to submit work to the graphics processor than the first data master and the second data master; and

resume executing work for the second data master based on designating the third data master with the higher priority.

7. The non-transitory program storage device of claim 6 , where the instructions further cause the one or more processors to:

determine an updated stall counter value for the third data master, wherein the updated stall counter value is indicative of a number of time periods the designated third data master has work to submit the graphics processor, but is unable to submit the work;

compare the updated stall counter value with a threshold value; and

generate a second notification to pause the first data master and the second data master based on a determination that the updated stall counter value satisfies the threshold value.

8. The non-transitory program storage device of claim 1 , wherein that notification to pause is a hardware driven notification that pauses all other data masters except the first data master within the priority list.

9. The non-transitory program storage device of claim 1 , wherein the first data master has the highest priority to submit work to the graphics processor amongst the plurality of data masters.

10. A system comprising:

memory; and

a graphics processor that interacts with the memory and includes a plurality of graphics hardware interfaces, wherein the graphics processor is configured to:

generate a priority list for the plurality of graphics hardware interfaces based on a comparison between actual utilizations for the graphics hardware interfaces and target utilizations for the graphics hardware interfaces

identify, based on the priority list, a first graphics hardware interface of the plurality of graphics hardware interfaces as a designated graphics hardware interface, wherein the designated graphics hardware interface has a higher priority to submit work to the graphics processor compared to a second graphics hardware interface of the plurality of graphics hardware interfaces;

determine an overall stall counter value for the designated graphics hardware interface, wherein the overall stall counter value is based on a set of stall counter values generated from a set of clusters within the graphics processor;

compare the overall stall counter value to a threshold value; and

generate a notification to pause execution of work for the second graphics hardware interface based on a determination that the overall stall counter value satisfies the threshold value.

11. The system of claim 10 , wherein the first graphics hardware interface and the second graphics hardware interface are associated with a first quality of service (QoS) layer.

12. The system of claim 11 , wherein a third graphics hardware interface of the plurality of graphics hardware interfaces are associated with a second QoS layer.

13. The system of claim 12 , wherein the notification to pause execution of work for the second graphics hardware interface is generated after pausing execution of work for the third graphics hardware interface.

14. The system of claim 10 , wherein the graphics processor is further configured to:

update the priority list after generating the notification to pause the second graphics hardware interface;

designate, based on the updated priority list, a third graphics hardware interface of the plurality of graphics hardware interfaces with a higher priority to submit work to the graphics processor than the first graphics hardware interface and the second graphics hardware interface; and

resume executing work for the second graphics hardware interface based on designating the third graphics hardware interface with the higher priority.

15. The system of claim 14 , wherein the graphics processor is further configured to:

determine a second overall stall counter value for the third graphics hardware interface, wherein the second overall stall counter value is indicative of a number of time periods the designated third graphics hardware interface has work to submit the graphics processor, but is unable to submit the work;

compare the second overall stall counter value with the threshold value; and

generate a third notification to pause the first graphics hardware interface and the second graphics hardware interface based on a determination that the second overall stall counter value satisfies the threshold value.

16. The system of claim 10 , wherein the graphics processor is further configured to:

send priority information indicating that the designated graphics hardware interface has a higher priority to a first cluster of the set of clusters; and

receive, based on the priority information, a first stall counter value of the set of stall counter values, wherein the first stall counter value is indicative of a number of time periods the first cluster is unable to process the work for the designated graphics hardware interface.

17. A computer-implemented method comprising:

generating a priority list for a plurality of data masters for graphics processor based on a comparison between a current utilizations for the data masters and a target utilizations for the data masters;

selecting, based on the priority list, a first data master of the plurality of data masters as a designated data master, wherein the designated data master has a higher priority to submit work to the graphics processor compared to a second data master of the plurality of data masters;

determining a stall counter value for the designated data master, wherein the stall counter value is indicative of a number of time periods the designated data master has work to submit to the graphics processor, but is unable to submit the work; and

generating a notification to pause work for the second data master based on the stall counter value.

18. The method of claim 17 , further comprising:

updating the priority list after generating the notification to pause the second data master;

designating, based on the updated priority list, a third data master of the plurality of data masters with a higher priority to submit work to the graphics processor than the first data master and the second data master; and

resuming executing work for the second data master based on designating the third data master with the higher priority.

19. The method of claim 18 , further comprising:

determining an updated stall counter value for the third data master, wherein the updated stall counter value is indicative of a number of time periods the designated third data master has work to submit the graphics processor, but is unable to submit the work;

comparing the updated stall counter value with a threshold value; and

generating a third notification to pause the first data master and the second data master based on a determination that the updated stall counter value satisfies the threshold value.

20. The method of claim 17 , wherein the number of time periods represents a number of graphics processor clock cycles during which the first data master has the work to submit the graphics processor, but is unable to submit the work.