Display device and method for driving the same
There is adopted a gate driver with a system of applying a direct current voltage as an active scanning signal to a gate bus line through a buffer transistor in a unit circuit that composes a shift register, and a display device is provided with a direct current voltage generation circuit that generates the direct current voltage. The direct current voltage generation circuit changes a voltage level of the direct current voltage in each frame period. For example, when a direct current voltage input terminal is provided on a vertical scanning end side, the direct current voltage generation circuit gradually decreases the voltage level of the direct current voltage in each frame period.
1. A display device comprising:
a display panel including: a plurality of scanning signal lines each being connected to a plurality of pixel formation portions; and a scanning signal line drive circuit configured to perform vertical scanning by sequentially turning the plurality of scanning signal lines to a selected state in each frame period; and
a direct current voltage generation circuit configured to generate a direct current voltage for turning the scanning signal lines to the selected state,
wherein
the display panel includes a direct current voltage input terminal configured to receive the direct current voltage generated by the direct current voltage generation circuit,
the scanning signal line drive circuit includes a shift register composed of a plurality of unit circuits provided to correspond to the plurality of scanning signal lines, the shift register being configured to perform a shift operation based on a plurality of clock signals,
each unit circuit includes:
a first output node configured to output a scanning signal to a corresponding scanning signal line;
a second output node configured to output a control signal for controlling operations of another unit circuit;
a first node configured to change from an OFF level to an ON level based on a control signal outputted from a second output node of another unit circuit;
a first output control transistor including a control terminal connected to the first node, a first conductive terminal connected to the direct current voltage input terminal, and a second conductive terminal connected to the first output node;
a second output control transistor including a control terminal connected to the first node, a first conductive terminal given a corresponding clock signal, and a second conductive terminal connected to the second output node;
a second node configured to change from an OFF level to an ON level based on a corresponding clock signal;
a second node turn-off transistor including a control terminal connected to the first node, a first conductive terminal connected to the second node, and a second conductive terminal given a potential of the OFF level;
a first first-output-node turn-off transistor including a control terminal connected to the second node, a first conductive terminal connected to the first output node, and a second conductive terminal given a potential of turning a scanning signal line to a non-selected state; and
a second first-output-node turn-off transistor including a control terminal connected to a second output node of an another unit circuit a first conductive terminal connected to the first output node, and a second conductive terminal given a potential of turning a scanning signal line to a non-selected state,
the direct current voltage generation circuit changes a voltage level of the direct current voltage in each frame period,
the potential given to the second conductive terminal of the first first-output-node turn-off transistor and the potential given to the second conductive terminal of the second first-output-node turn-off transistor are different from each other,
the first first-output-node turn-off transistor and the second first-output-node turn-off transistor are n-channel transistors, and
the potential given to the second conductive terminal of the second first-output-node turn-off transistor is lower than the potential iven to the second conductive terminal of the first first-output-node turn-off transistor.
2. The display device according to claim 1 , wherein
the direct current voltage generation circuit sets a voltage level of the direct current voltage when a scanning signal line disposed at a most distant position from the direct current voltage input terminal is to be turned to the selected state higher than a voltage level of the direct current voltage when a scanning signal line disposed at a closest position from the direct current voltage input terminal is to be turned to the selected state.
3. The display device according to claim 1 , wherein
the direct current voltage input terminal is provided so that the scanning signal line drive circuit is given the direct current voltage from a vertical scanning end side.
4. The display device according to claim 3 , wherein
the direct current voltage generation circuit gradually decreases the voltage level of the direct current voltage in each frame period.
5. The display device according to claim 3 , wherein
the direct current voltage generation circuit decreases the voltage level of the direct current voltage step by step in each frame period so that a voltage level of the direct current voltage when a scanning signal line whose order of vertical scanning is M-th (M is an integer not less than 2 and not more than a number of the plurality of scanning signal lines) is to be turned to the selected state is not more than a voltage level of the direct current voltage when a scanning signal line whose order of vertical scanning is (M−1)-th is to be turned to the selected state.
6. The display device according to claim 1 , wherein
the display panel includes, as the direct current voltage input terminal, a first direct current voltage input terminal configured to give the direct current voltage to the scanning signal line drive circuit from a vertical scanning start side, and a second direct current voltage input terminal configured to give the direct current voltage to the scanning signal line drive circuit from a vertical scanning end side.
7. The display device according to claim 6 , wherein,
in each frame period, the direct current voltage generation circuit gradually decreases the voltage level of the direct current voltage after gradually raising the voltage level of the direct current voltage.
8. The display device according to claim 1 , wherein
a frequency of the voltage level of the direct current voltage is equal to a frame frequency.
9. The display device according to claim 1 , wherein
the direct current voltage generation circuit changes an amount of change in the voltage level of the direct current voltage in each frame period depending on an accumulated operation time of the display panel.
10. The display device according to claim 1 , wherein
a period corresponding to a pulse with of the plurality of clock signals is longer than one horizontal scanning period.
11. The display device according to claim 1 , wherein
channel layers of the first output control transistor and the second output control transistor are formed by using an oxide semiconductor.
12. A method for driving a display device including a display panel having: a plurality of scanning signal lines each being connected to a plurality of pixel formation portions; and a scanning signal line drive circuit configured to perform vertical scanning by sequentially turning the plurality of scanning signal lines to a selected state in each frame period, the method comprising:
a scanning signal line driving step of causing the scanning signal line drive circuit to sequentially turn the plurality of scanning signal lines to a selected state; and
a direct current voltage generation step of generating a direct current voltage for turning the scanning signal lines to the selected state,
wherein
the display panel includes a direct current voltage input terminal configured to receive the direct current voltage generated in the direct current voltage generation step,
the scanning signal line drive circuit includes a shift register composed of a plurality of unit circuits provided to correspond to the plurality of scanning signal lines, the shift register being configured to perform a shift operation based on a plurality of clock signals,
each unit circuit includes:
a first output node configured to output a scanning signal to a corresponding scanning signal line;
a second output node configured to output a control signal for controlling operations of another unit circuit;
a first node configured to change from an OFF level to an ON level based on a control signal outputted from second output node of another unit circuit;
a first output control transistor including a control terminal connected to the first node, a first conductive terminal connected to the direct current voltage input terminal, and a second conductive terminal connected to the first output node;
a second output control transistor including a control terminal connected to the first node, a first conductive terminal given a corresponding clock signal, and a second conductive terminal connected to the second output node;
a second node configured to change from an OFF level to an ON level based on a corresponding clock signal;
a second node turn-off transistor including a control terminal connected to the first node a first conductive terminal connected to the second node and a second conductive terminal given a potential of the OFF level;
a first first-output-node turn-off transistor including a control terminal connected to the second node, a first conductive terminal connected to the first output node, and a second conductive terminal given a potential of turning a scanning signal line to a non-selected state; and
a second first-output-node turn-off transistor including a control terminal connected to a second output node of an another unit circuit, a first conductive terminal connected to the first output node, and a second conductive terminal given a potential of turning a scanning signal line to a non-selected state,
the voltage level of the direct current voltage generated in the direct current voltage generation step changes in each frame period,
the potential given to the second conductive terminal of the first first-output-node turn-off transistor and the potential given to the second conductive terminal of the second first-output-node turn-off transistor are different from each other,
the first first-output-node turn-off transistor and the second first-output-node turn-off transistor are n-channel transistors, and
the potential given to the second conductive terminal of the second first-output-node turn-off transistor is lower than the potential given to the second conductive terminal of the first first-output-node turn-off transistor.