Method for hybrid wafer-to-wafer bonding
View Patent ↗A method for hybrid wafer-to-wafer bonding, comprising: providing two silicon wafers with Cu pattern structures, a conventional Cu BEOL process is adopted on the silicon wafers to obtain the planarized surface with copper and dielectric; removing part of the Cu on the planarized surface of the Cu pattern structures by adopting an etching process to form a certain amount of Cu recesses; depositing a layer of bonding metal on the surface of the Cu by adopting a selective deposition process; performing surface activation on the bonding metal and the dielectric by adopting a surface activation process; aligning and pressing the two silicon wafers together to obtain the dielectric bonding; and obtaining the metal bonding through the annealing process. The sufficient metal bonding can be obtained at low annealing temperature according to the present invent, thereby the risk of dielectric delaminating caused by thermal expansion mismatch is reduced, which is conducive to reduce the difficulty of process integration, save process time and improve product yield.
1. A method for hybrid wafer-to-wafer bonding, wherein comprises the following steps in sequence:
S 01 : providing two silicon wafers with Cu pattern structures, wherein each of the silicon wafers has a planarized surface with copper and dielectric by a conventional Cu BEOL process;
S 02 : removing part of the copper on the planarized surface of the Cu pattern structure on each of the silicon wafers by adopting an etching process to form a certain amount of copper recesses;
S 03 : separately depositing a layer of bonding metal on the surface of the copper on each of the silicon wafers by adopting a selective deposition process before aligning and bonding the two silicon wafers;
S 04 : performing surface activation on the bonding metal and the dielectric on each of the silicon wafers by adopting a surface activation process;
S 05 : aligning and pressing the two silicon wafers together to obtain the dielectric bonding;
S 06 , obtaining the metal bonding through the annealing process.
2. The method for hybrid wafer-to-wafer bonding according to claim 1 , wherein, the S 01 comprises the following steps: depositing a layer of the dielectric on the surface of the silicon wafer substrates; adopting a photo lithography and an etching process to obtain Pad trenches; and performing a PVD process to deposit a barrier layer and a seed layer on the Pad trenches; the copper is filled by an ECP process, and a planarization surface of the copper and the dielectric is obtained by adopting a CMP process.
3. The method for hybrid wafer-to-wafer bonding according to claim 1 , wherein the S 02 comprises the following step: removing part of the copper by adopting a wet etching process.
4. The method for hybrid wafer-to-wafer bonding according to claim 1 , wherein, the S 02 comprises the following step: oxidizing the surface of the copper by adopting an oxidation process and removing the oxidized copper by adopting a wet etching process.
5. The method for hybrid wafer-to-wafer bonding according to claim 1 , wherein, in the S 03 , a electroless plating process is adopted to deposit the bonding metal on the copper surface.
6. The method for hybrid wafer-to-wafer bonding according to claim 1 , wherein, the bonding metal is Sn or Au.
7. The method for hybrid wafer-to-wafer bonding according to claim 1 , wherein, after the bonding metal is deposited in the S 03 , the height of the bonding metal is not higher than the height of the dielectric.
8. The method for hybrid wafer-to-wafer bonding according to claim 1 , wherein, the S 04 comprises the following steps: firstly, activating the bonding metal and the dielectric by adopting plasma bombardment, and then carrying out surface cleaning by adopting a wet cleaning process.
9. The method for hybrid wafer-to-wafer bonding according to claim 1 , wherein, the dielectric bonding in the S 05 is obtained at room temperature and normal pressure.
10. The method for hybrid wafer-to-wafer bonding according to claim 1 , wherein, the annealing process temperature of the S 06 is within 200° C.