Method of manufacturing a semiconductor device

1. A method of manufacturing a semiconductor device, the method comprising:

providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface of the gate electrode is leveled with the first surface;

forming an alignment layer over the first surface of the wafer and the top surface of the gate electrode;

forming a photoresist on the alignment layer to cover a portion of the top surface of the gate electrode;

removing portions of the alignment layer uncovered by the photoresist to form an alignment structure on the top surface of the gate electrode;

forming a dielectric surrounding the alignment structure on the first surface;

removing the alignment structure to expose at least a portion of the gate electrode; and

forming a gate conductor over and in contact with the gate electrode.

2. The method of claim 1 , wherein the gate conductor is embedded in the dielectric.

3. The method of claim 1 , wherein the dielectric is made with a material different from the material of the alignment structure.

4. The method of claim 1 , wherein the alignment structure includes polysilicon.

5. The method of claim 1 , further comprising:

forming a first alignment structure on a portion of the top surface of the gate electrode; and

forming a second alignment structure connected to the first alignment structure to form the alignment structure on the top surface of the gate electrode.

6. The method of claim 1 , wherein after the alignment structure is removed, an opening is formed in the dielectric, and the gate conductor is formed by filling the opening with a conductive material.

7. The method of claim 1 , wherein the gate electrode includes more than one metal layer.

8. The method of claim 1 , wherein the wafer further includes a first spacer and a second spacer on opposite sides of the gate electrode and embedded in a first inter-layer dielectric (ILD) of the wafer, wherein a side of the first spacer facing away from the gate electrode and a side of the second spacer facing away from the gate electrode define a first area of the first surface, and the alignment structure is formed on the first area.

9. The method of claim 1 , wherein the wafer further includes a source/drain region embedded in a first inter-layer dielectric (ILD) of the wafer, and the method further comprises:

forming a source conductor and a drain conductor after the gate conductor is formed.

10. The method of claim 9 , wherein the source/drain regions are located on opposite sides of the gate electrode.

11. A method of manufacturing a semiconductor device, the method comprising:

providing a wafer having a first surface, a gate electrode and a source/drain region wherein the gate electrode has a top surface, and the top surface of the gate electrode is leveled with the first surface of the wafer;

disposing an alignment structure over the top surface of the gate electrode and the source/drain region to overlap at least a portion of the gate electrode without covering the source/drain region from a top view;

forming a dielectric on the first surface to surround the alignment structure, wherein the dielectric is made with a material different from the material of the alignment structure;

removing the alignment structure to expose the overlapped portion of the gate electrode; and

forming a gate conductor over and in contact with the exposed gate electrode.

12. The method of claim 11 , wherein the gate conductor is embedded in the dielectric.

13. The method of claim 11 , further comprising:

forming a first alignment structure on at least a portion of the gate electrode without covering the source/drain region from a top view; and

forming a second alignment structure connected to the first alignment structure to form the alignment structure.

14. The method of claim 11 , wherein after the alignment structure is removed, an opening is formed in the dielectric, and the gate conductor is formed by filling the opening with a conductive material.

15. The method of claim 11 , wherein the wafer has a first surface, the gate electrode has a top surface, the top surface of the gate electrode is leveled with the first surface, and the alignment structure is disposed in at least a portion of the top surface of the gate electrode.

16. The method of claim 11 , wherein the alignment structure includes polysilicon.

17. The method of claim 11 , further comprising:

forming a first alignment structure over the gate electrode and the source/drain region to overlap at least a portion of the gate electrode without covering the source/drain region from a top view; and

forming a second alignment structure connected to the first alignment structure to form the alignment structure over the gate electrode and the source/drain region to overlap at least a portion of the gate electrode without covering the source/drain region from a top view.

18. A method of manufacturing a semiconductor device, the method comprising:

providing a wafer having a substrate and a gate electrode, wherein the gate electrode is an elongated structure along a first direction extending over the substrate;

disposing an elongated alignment structure along the first direction extending over the gate electrode, wherein the alignment structure leaves a portion of a source/drain region uncovered, the source/drain region is located on opposite sides of the gate electrode along a second direction, and the first direction is perpendicular to the second direction;

removing at least a portion of the elongated alignment structure and leaving an alignment structure;

forming a dielectric surrounding the alignment structure, wherein the dielectric is made with a material different from the material of the alignment structure;

removing the alignment structure to expose at least a portion of the gate electrode; and

forming a gate conductor in contact with the exposed gate electrode.

19. The method of claim 18 , wherein the alignment structure includes polysilicon.

20. The method of claim 18 , wherein the gate conductor is embedded in the dielectric.